TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 217

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

STATUS [2:0]
(Bit4 to bit2)
000: READY
001: DATAIN
010: FULL
011: TX_ERR
100: RX_ERR
101: BUSY
110: STALL
111: INVALID
Receiving:
Transmitting:
This status is used only for the control transfer type and it is set when a
status-stage token is received from the host after a terminated data-stage.
When status-stage can be finished, terminates correctly and returns to READY.
This is not used in the Bulk and interrupts transfer type.
This status shows that the corresponding endpoint is in STALL status.
In this status, STALL-handshake returns, except for SETUP-token. The control
endpoint returns to READY from stall condition when SETUP-token is received.
Other endpoints return to READY when initialization command of FIFO is
received.
(Note) With Automatic Set_Interface request answer, requests to interface 4 to 6
may not become request errors. If this is a problem, in Set_Interface request
answer, set Standard Request Mode <S_INTERFACE> to “1” and use software.
This status shows that the corresponding endpoint is in UNCONFIGURED
status.
In this status, the UDC has no effect when a token is received from the host.
On reset, all endpoints are set to INVALID status. Only endpoint 0 returns to
READY on receiving USB-reset. Corresponding endpoints return to READY
according to configuration.
Device can be received.
In endpoints 1 to 7, this register is initialized to “READY” by setting transfer type at
SET_CONFIGURATION.
In endpoint 0, this register is initialized to “READY” by detecting USB reset from the
host.
This is initialized to “READY” by terminating the status stage without error.
Basically, the same as “Receiving”.
But in transmitting, when data for transmission is set to FIFO and answer to token
from host and transfer data to host collect and received ACK, status register does not
change, and it remains “READY”. In this case, EPx_Empty_A or EPx_Empty_B
interrupt terminate the transfer correctly.
UDC set to DATAIN and generates EPx_FULL_A or EPx_FULL_B interrupt when
data is received from the host without error.
Refer to 3.10.8 (2) Details for the STATUS register.
After transfer of data to IN token from host, UDC sets TX-ER to status register when
“ACK” is not received from host. In this case, an interrupt is not generated. The hosts
re-try IN token transfer.
UDC sets RX_ERR to status register without transmitting “ACK” to host when an
error (such as a CRC-error) is detected in data of received token. In this case, an
interrupt is not generated. The hosts re-try IN token transfer.
results of the transfer. . These depend on transfer type.
92CH21-215
These bits show status of UDC endpoint.
The status shows whether transfer is possible or not, and the
(For the Isochronous transfer type, refer to 3.10.6.)
TMP92CH21
2009-06-19