TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 102

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

PJCR
(004EH)
PJFC
(004FH)
PJDR
(0093H)
PJ
(004CH)
Note: Read-modify-write is prohibited for the registers PJCR and PJFC.
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Bit symbol
Read/Write
Reset State
Function
0: Port
1: SDCKE
PJ7F
PJ7D
PJ7
0
1
1
7
7
7
7
(Output latch register is set
0: Port
1: NDCLE at
Data from external port
<PJ6> = 0,
SDUUDQM
at
<PJ6> = 1
PJ6C
PJ6F
PJ6D
PJ6
0: Input 1: Output
0
1
6
6
6
0
6
Figure 3.5.40 Register for Port J
to “1”)
Port J Function Register
Port J Control Register
W
Port J Drive Register
0: Port
1: NDALE at
Input/Output buffer drive register for standby mode
Port J Register
<PJ5> = 0,
SDULDQM
at
<PJ5> = 1
PJ5C
PJ5F
PJ5D
92CH21-100
PJ5
0
1
5
5
0
5
5
0: Port
1: SDLUDQM
PJ4D
PJ4F
PJ4
0
1
4
4
4
1
4
R/W
R/W
W
0: Port
1: SDLLDQM
PJ3D
PJ3F
PJ3
0
1
3
3
3
1
3
0: Port
1
:
SDWE
SDWR
PJ2D
PJ2F
PJ2
0
2
1
2
2
1
2
,
0: Port
1
:
SRLUB
SDCAS
PJ1F
PJ1D
PJ1
0
1
1
1
1
1
1
TMP92CH21
2009-06-19
,
0: Port
1
:
SRRAS
SRLLB
PJ0D
PJ0F
PJ0
0
1
0
0
0
1
0
,