TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 249

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

(a-1) Transmission bulk mode
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The token packet is received and the address endpoint number error is confirmed,
and it checks whether the relevant endpoint transfer mode corresponds with the
IN token. If it does not correspond, the state returns to IDLE.
Condition of EPx_STATUS register is confirmed.
handshake is returned, and state returns to IDLE.
Data packet is generated.
generated. At this point, the transferred data number is confirmed. And if there is
more than the maximum payload size of each endpoint, bit stuff error is generated,
transfer is finished, and STATUS becomes STALL.
CRC bit (counted transfer data of FIFO from first to last) is attached to last.
When ACK handshake from host is received,
Below is the transaction format for bulk transfer during transmitting.
Control flow
FIFO condition is confirmed, if data number of 1 packet is not prepared, NAK
If data number of 1 packet is prepared to FIFO, it shifts to 3.
Next, data is transferred from FIFO of internal UDC to SIE, and data packet is
UDC finishes normally. FIFO can receive the next data.
If a time out occurs without receiving ACK from host,
Execute above setting. And wait next retry keeping FIFO data.
This flow is shown in Figure 3.10.3.
Data packet generated by using toggle bit register in UDC.
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Below is the control-flow when the UDC receives an IN token.
Clear FIFO.
Clear DATASET register.
Renew toggle bit, and prepare for next.
Set STATUS to READY.
Set STATUS to TX_ERR.
Return FIFO address pointer.
Token: IN
Data: DATA0/DATA1, NAK, STALL
Handshake: ACK
INVALID condition: State returns to IDLE.
STALL condition: Stall handshake is returned and state returns to IDLE.
92CH21-247
TMP92CH21
2009-06-19