TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 199

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

USBINTFR1
(07F0H)
bit Symbol
Read/Write
Reset State
Function
Note: The above interrupts can release Halt state from IDLE2 and IDLE1 mode. (STOP mode cannot be released)
INT_URST_STR
*Those 6 interrupts of all 24 INTUSB sources can release Halt state from IDLE1 mode. Therefore, a low power
dissipation system can be built. However, the method of use is limited as below.
Shift to IDLE1 mode :
Release from IDLE1 mode :
When read 0: Not generate interrupt
R/W
7
0
•
•
•
•
•
•
INT_URST_STR (Bit7)
INT_URST_END (Bit6)
INT_SUS (Bit5)
INT_RESUME (Bit4)
INT_CLKSTOP (Bit3)
INT_CLKON (Bit2)
USB-host.
USB-host.
supply - interrupt).
USBCR1<USBCLKE> to “0” to stop the clock after detecting this interrupt if
needed.
- interrupt).
to receive a “USB reset” signal from a USB-host. In case the clock has be
stopped, set USBCR1<USBCLKE> to “1” to start the clock after detecting this
interrupt if needed.
Execute Halt instruction when the INT_SUS or INT_CLKSTOP flag is “1” (SUSPEND state)
Release Halt state by INT_RESUME or INT_CLKON request (request of release SUSPEND)
Release Halt state by INT_URST_STR or INT_URST_END request (request of RESET)
1: Generate interrupt
INT_URST_END
This is the flag register for INT_URST_STR (“USB reset” start - interrupt).
This is set to “1” when the UDC starts to receive a “USB reset” signal from a
An application program has to initialize the whole UDC with this interrupt.
This is the flag register for INT_URST_END (“USB reset” end - interrupt).
This is set to “1” when the UDC receives a “USB reset end” signal from a
This is the flag register for INT_SUS (suspend - interrupt).
This is set to “1” when the USB changes to “suspend status”.
This is the flag register for INT_RESUME (resume - interrupt).
This is set to “1” when the USB changes to “resume status”.
This is the flag register for INT_CLKSTOP (enables stopping of the clock
This is set to “1” after the USB changes to “suspend status”. Set
This is the flag register for INT_CLKON (enable starting of the clock supply
This is set to “1” after changing to “resume status” or when the UDC started
R/W
6
0
INT_SUS
R/W
5
0
92CH21-197
When write
INT_RESUME
R/W
4
0
1: −
0: Clear flag
INT_CLKSTOP
R/W
0
3
INT_CLKON
R/W
2
0
1
TMP92CH21
2009-06-19
0