TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 101

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

3.5.14
Port J (PJ0 to PJ7)
they output “1”. PJ5 to PJ6 are 2-bit I/O ports.
(
SRAM (
automatically according to the setting of the memory controller.
SDRAS
PJ0 to PJ4 and PJ7 are 6-bit output ports. Resetting sets the output latch PJ to “1”, and
In addition to functioning as a port, port J also functions as output pins for SDRAM
The above settings are made using the function register PJFC.
However, H either SDRAM or SRAM output signals for PJ0 to PJ2 are selected
SDULDQM, SDUUDQM
Reset
,
SRWR
SDCAS
NDALE, NDCLE
Direction control
Function control
Function control
PJFC2 write
Output latch
Output latch
,
PJFC write
PJ read
PJFC write
PJ read
PJCRwrite
SRLLB SRLUB
PJ write
PJ write
,
Reset
SDWE
Figure 3.5.38 Port J0, J1, J2, J3, J4 and J7
S
, SDLLDQM, SDLUDQM, SDULDQM, SDUUDQM and SDCKE),
Figure 3.5.39 Port J5 and J6
) and NAND flash (NDALE and NDCLE).
92CH21-99
Selector
Selector
Selector
S
S
S
SRLLB
SDRAS
B
A
,
,
SRLUB
SDCAS
,
,
SRWR
SDWE
, SDLLDQM, SDLUDQM, SDCKE
PJ0 (
PJ1 (
PJ2 (
PJ3 (SDLLDQM)
PJ4 (SDLUDQM)
PJ7 (SDCKE)
SDRAS
SDCAS
SDWE
,
,
,
SRWR
SRLLB
SRLUB
PJ5 (SDULDQM, NDALE),
PJ6 (SDUUDQM, NDCLE)
)
)
)
TMP92CH21
2009-06-19