TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 181

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

Figure 3.9.19 Transmitting Operation in I/O Interface Mode (SCLK0 output mode) (Channel 0)
Figure 3.9.20 Transmitting Operation in I/O Interface Mode (SCLK0 input mode) (Channel 0)
When all data is output, INTES0<ITX0C> will be set to generate an INTTX0 interrupt.
SCLK0 output
(<SCLKS> = 0:
rising edge mode)
SCLK0 output
(<SCLKS> = 1:
falling edge mode)
TXD0
Timing of transmitted
data writing
ITX0C
(INTTX0 interrupt
request)
1.
SCLK0 input
(<SCLKS> = 0:
rising edge mode)
SCLK0 input
(<SCLKS> = 1:
falling edge mode)
TXD0
ITX0C
(INTTX0 intterrupt
reqest)
Transmission
TXD0 and SCLK0 pins respectively each time the CPU writes data to the
transmission buffer. When all data is output, INTES0<ITX0C> will be set to
generate the INTTX0 interrupt.
input becomes active after the data has been written to the transmission buffer by
the CPU.
In SCLK output mode 8-bit data and a synchronous clock are output on the
In SCLK input mode, 8-bit data is output on the TXD0 pin when the SCLK0
Bit0
92CH21-179
Bit0
Bit1
Bit1
Bit5
Bit6
Bit6
Bit7
Bit7
TMP92CH21
2009-06-19
(Internal
Clock timing)