TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 165
TMP92xy21FG
Manufacturer Part Number
TMP92xy21FG
Description
Manufacturer
Toshiba
Datasheet
1.TMP92XY21FG.pdf
(544 pages)
Specifications of TMP92xy21FG
Package
LQFP144
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
16
Architecture
32-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
-
(s)dram Controller
1
Adc 10-bit Channel
4
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
1
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
82
Power Supply Voltage(v)
3.0 to 3.6
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•
•
Integer divider (N divider)
clock is φT2 (f
BR0CR<BR0ADDE> = 0, the baud rate in UART mode is as follows:
= 39.3216 × 10
N + (16 − K)/16 divider (UART mode only)
is
(BR0ADD<BR0K3:0>) = 8, and BR0CR<BR0ADDE> = 1, the baud rate in UART
mode is as follows:
channels 0 and 1). The method for calculating the baud rate is explained below:
* Clock condition Clock gear
* Clock condition Clock gear
Note: The N + (16 − K)/16 division function is disabled and setting
Baud rate =
•
•
Baud rate =
For example, when the source clock frequency (f
Accordingly, when the source clock frequency (f
Table 3.9.3 show examples of UART mode transfer rates.
Additionally, the external clock input is available in the serial clock. (Serial
φT2
In UART mode
In I/O interface mode
Baud rate = external clock input frequency ÷ 16
It is necessary to satisfy (External clock input cycle) ≥ 4/f
Baud rate = external clock input frequency
It is necessary to satisfy (External clock input cycle) ≥ 16/f
BR0ADD<BR0K3:0> is invalid.
(f
C
= 6 +
= 31.9488 × 10
=
/32),
6
Frequency divider for baud rate generator
÷ 16 ÷ 8 ÷ 16 = 9600 (bps)
Frequency divider for baud rate generator
C
f
/32), the frequency divider N (BR0CR<BR0S3:0>) = 8, and
C
Input clock of baud rate generator
8
/32
the
Input clock of baud rate generator
f
C
92CH21-163
/32
(16 − 8)
frequency
÷ 16
6
16
÷ 16 ÷ (6 + 16 ) ÷ 16 = 9600 (bps)
: 1/1
: 1/1
÷ 16
divider
8
N
C
) = 31.9488 MHz, the input clock
(BR0CR<BR0S3:0>)
C
) is 39.3216 MHz, the input
÷ 16
÷ 16
SYS
SYS
TMP92CH21
2009-06-19
=
6,
K
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