TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 475

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TMP92xy21FG

Manufacturer Part Number
TMP92xy21FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy21FG

Package
LQFP144
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
16
Architecture
32-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
-
(s)dram Controller
1
Adc 10-bit Channel
4
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
1
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
82
Power Supply Voltage(v)
3.0 to 3.6
No.
4.3.2
1 System clock period ( = T)
2 A0, A1 → D0 to D31 input
3 A2 to A23 → D0 to D31 input
4
5 A0 to A23 Invalid → D0 to D31 hold
6
AC measuring condition
D0 to D31
A0 to A23
RD
RD
SDCLK
• Output: High = 0.7 VCC, Low = 0.3 VCC, C
• Input: High = 0.9 VCC, Low = 0.1 VCC
falling → D0 to D31 input
rising → D0 to D31 hold
CS
RD
2
Page ROM Read Cycle
(1) 3-2-2-2 mode
Parameter
t
CYC
t
AD3
t
RD3
+0
Data
input
Symbol
t
t
t
t
CYC
AD2
AD3
RD3
t
t
HA
HR
L
92CH21-473
= 50 pF
t
t
HA
AD2
+1
Data
input
Min
50
0
0
Variable
t
t
HA
2.0T − 50
3.0T − 50
2.5T − 45
AD2
166.7
Max
+2
Data
input
40 MHz 36 MHz 27 MHz Unit
100
50
50
80
0
0
t
t
HA
AD2
+3
116.5
55.5
93.8
61
0
0
Data
input
t
t
HA
HR
TMP92CH21
172
140
74
98
0
0
2009-06-19
ns

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