TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 424

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

3.18.4
Match with TB0RG0H/L
Match with TB0RG1H/L
(Value to be compared)
X: Don't care, −: No change
TB0RUN
INTETB01
TB0FFCR
TB0MOD
TB0RUN
TB0RG1H/L
Operation in Each Mode
(1) 16-bit interval timer mode
(2) 16-bit programmable pulse generation (PPG) output mode
Figure 3.18.6 Programmable Pulse Generation (PPG) Output Waveforms
Register buffer
In this example, the interrupt INTTB01 is set to be generated at fixed intervals. The
interval time is set in the timer register TB0RG1H/L.
pulse may be either low active or high active.
by the match of the up counter UC10 with timer register TB0RG0H/L or TB0RG1H/L
and is output to TB0OUT0. In this mode the following conditions must be satisfied.
buffer 10 will be shifted into TB0RG0H/L at match with TB0RG1H/L. This feature
facilitates the handling of low duty waves.
Match with TB0RG0H/L
Match with TB0RG1H/L
TB0RG0H/L
Generating interrupts at fixed intervals.
Square wave pulses can be generated at any frequency and duty ratio. The output
The PPG mode is obtained by inversion of the timer flip-flop TB0FF0 that is enabled
(Value set in TB0RG0H/L) < (Value set in TB0RG1H/L)
When the TB0RG0H/L double buffer is enabled in this mode, the value of register
(INTTB01 interrupt)
(INTTB00 inerrupt)
← 0
← X
← 1
← 0
← *
← 0
TB0OUT0 pin
7
*
1
1
0
6
0
*
*
0
Figure 3.18.7 Operation of Register Buffer
X
X
5
0
0
1
*
*
Up counter = Q
X
X
4
0
0
0
*
*
X
3
−
0
0
*
*
−
(** = 01, 10, 11)
2
0
0
0
1
1
*
*
Q
92CH21-422
1
X
X
1
0
1
*
*
*
1
0
0
0
1
*
*
*
1
Q
Stop TMRB0.
Enable INTTB01 and set interrupt level 4. Disable INTTB00.
Disable the trigger.
Select internal clock for input and disable the capture function.
Set the interval time (16 bits).
Start TMRB0.
2
Shift into TB0RG1H/L
Up counter = Q
Write TB0RG0H/L
Q
2
2
Q
3
TMP92CH21
2009-06-19