TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 388

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

SRS2
0
0
0
0
1
1
1
1
SDRCR<SRS2:0>
Note: A system reset disables the Auto-Refresh function.
SRS1
(3) Refresh control
0
0
1
1
0
0
1
1
(a) Auto-refresh
This LSI supports two refresh commands: auto-refresh and self-refresh.
SDRCR<SRS2:0> by setting SDRCR<SRC> to “1”. The generation interval can be
set from between 47 to 312 states (2.4 μs to 15.6 μs at f
auto-refresh command. The auto-refresh cycle is shown in Figure 3.16.4 and the
auto-refresh generation interval is shown in Table 3.16.2. The Auto-Refresh
function cannot be used in IDLE1 and STOP modes. In these modes, use the Self-
Refresh function to be explained next.
SRS0
The auto-refresh command is automatically generated at intervals set by
CPU operation (instruction fetch and execution) stops while performing the
0
1
0
1
0
1
0
1
Table 3.16.2
Figure 3.16.4
Insertion
Interval
(State)
124
156
195
249
312
47
78
97
SDUUDQM
SDULDQM
SDLUDQM
SDCAS
SDWE
SDLLDQM
SDRAS
SDCS
SDCKE
SDCLK
Refresh Cycle Insertion Interval
Timing of Auto-Refresh Cycle
6 MHz
92CH21-386
13.0
16.2
20.7
26.0
32.5
41.5
52.0
7.8
10 MHz 12.5 MHz 15 MHz 17.5 MHz 20 MHz
Auto-refresh
2 states
12.4
15.6
19.5
24.9
31.2
f
4.7
7.8
9.7
SYS
Frequency (System clock)
12.5
15.6
19.9
25.0
3.8
6.2
7.8
9.9
10.4
13.0
16.6
20.8
3.1
5.2
6.5
8.3
SYS
= 20 MHz).
11.1
14.2
17.8
2.7
4.5
5.5
7.1
8.9
TMP92CH21
2009-06-19
(Unit: μs)
12.4
15.6
2.4
3.9
4.9
6.2
7.8
9.8