TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 525

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

SC0MOD0
SC0MOD1
Symbol
BR0ADD
SC0BUF
SC0CR
BR0CR
SIRCR
(11) UART/serial channel (1/2)
channel 0
channel 0
channel 0
channel 0
channel 0
channel 0
baud rate
K setting
Name
register
register
mode 0
register
register
register
mode 1
register
register
control
control
control
Serial
buffer
Serial
Serial
Serial
Serial
Serial
IrDA
Address
(Prohibit
1200H
1201H
1202H
1203H
1204H
1205H
1207H
RMW)
Receive
data bit8
Trans-
mission
data bit8
Always
write “0”
IDLE2
0: Stop
1: Operate
Select
transmit
pulse
width
0: 3/16
1: 1/16
Undefined
PLSEL
I2S0
RB7
RB8
R/W
TB7
TB8
R
7
0
−
0
0
0
BR0ADDE BR0CK1
Parity
0: Odd
1: Even
0: CTS
1: CTS
(16-K)/16
divided
0: Disable
1: Enable
Duplex
0: Half duplex
1: Full duplex
Receive
data
0: “H” pulse
1: “L” pulse
FDPX0
RXSEL
EVEN
CTSE
disable
enable
RB6
R/W
TB6
6
0
0
0
0
0
92CH21-523
R/W
Parity
0: Disable
1: Enable
0: Receive
1: Receive
00: φT0
01: φT2
10: φT8
11: φT32
Transmit
0: Disable
1: Enable
TXEN
disable
enable
RXE
RB5
TB5
PE
5
0
0
0
0
R (Receiving)/W (Transmission)
Overrun
Wake-up
0: Disable
1: Enable
Receive
0: Disable
1: Enable
BR0CK0
OERR
RXEN
RB4
TB4
WU
4
0
0
0
0
R (Clear 0 after reading)
Undefined
R/W
R/W
00: I/O Interface mode
Parity
01: 7-bit UART mode
10: 8-bit UART mode
11: 9-bit UART mode
Select receive pulse width
Set effective pulse width for equal or more
than 2x × (value + 1) + 100ns
Can be set: 1 to 14
Can not be set: 0,15
SIRWD3
1: Error
BR0S3
BR0K3
PERR
RB3
SM1
R/W
TB3
3
0
0
0
0
0
(divided by N + (16 − K)/16).
Sets frequency divisor “K”
Divided frequency setting
Framing
SIRWD2
BR0S2
BR0K2
FERR
SM0
RB2
TB2
2
0
0
0
0
0
R/W
0: SCLK0 ↑
1: SCLK0 ↓
00: TA0TRG
01: Baud rate
10: Internal clock f
11: External clock
SIRWD1
SCLKS
BR0S1
BR0K1
RB1
SC1
TB1
1
0
0
generator
(SCLK0 input)
0
0
0
TMP92CH21
2009-06-19
R/W
0: Baud
1: SCLK0
SIRWD0
BR0S0
BR0K0
rate
generator
pin input
RB0
SC0
TB0
IOC
0
0
0
0
0
0
IO