TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 157

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

3.8.3
•
•
•
•
Setting Example
(a) Main routine (COMMON-Z)
C00000H
C000xxH
C000yyH
Address
No.
Logical
Below is a setting example.
(a)
(b)
(c)
(d)
(e)
Instructions from No.2 to No.8 are settings for ports and memory controller.
No.9 is a setting for stack pointer. It is assigned to internal RAM.
No.10 is a setting to execute No.12’s instruction.
No.12 is an instruction to call sub routine. When CPU outputs 400000H address, this MMU
will convert and output 000000H address to external address bus: A23 to A0. And
SRAM will be asserted because its logical address is in the CS1area at the same time.
These instructions allow the CPU to branch to sub routine.
(Note) This example assumes a sub routine program is already written on SRAM.
display RAM
Used as
Character
routine
routine
← (Same)
←
←
Physical
Address
Stack
ROM
Main
RAM
LCD
Sub
No
Internal RAM
5.1
5.2
10
11
12
13
14
15
(16 Mbytes,
(16 Mbytes,
(16 Kbytes)
1
2
3
4
5
6
7
8
9
NOR flash
Memory
SRAM
1 pcs)
1 pcs)
org
ldw
ldw
ldw
ldw
ld
ld
ld
ld
ld
ld
ld
:
call
:
:
:
92CH21-155
C00000H
(mamr2), 80FFH
(b2csl), C222H
(mamr1), 40FFH
(b1csl), 8111H
(localpz), 80H
(localrz), 80H
(p8fc), 02H
(p8fc2), 04H
(pjfc), 07H
xsp, 6000H
(localpy), 80H
400000H
(32 bits, 1 clock)
Instruction
Setting
32 bits,
16 bits,
0 waits
CSZA
1 wait
CS
−
1
,
,
MMU Area
COMMON-Z
LOCAL-Z
LOCAL-Y
LOCAL-Y
LOCAL-Y
Bank 0 in
Bank 0 in
Bank 1 in
Bank 2 in
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
CS2 800000-FFFFFF/8 Mbytes
CS2 32-bit ROM, 1 wait
CS1 400000-7FFFFF/4 Mbytes
LOCAL-Z bank enable for program
LOCAL-Z bank enable for data read
P81:
P82:
PJ2:
Stack pointer = 6000H
BANK 0 in LOCAL-Y is set as program for
sub routine
Call sub routine
CS1 16-bit RAM, 0 waits
SRWR
CS
CSZA
800000H to
400000H to
Address
BFFFFFH
5FFFFFH
Logical
1
C00000H to FFFFFFH
002000H to 005FFFH
, PJ1:
Comment
SRLUB
000000H to
000000H to
200000H to
Physical
Address
3FFFFFH
1FFFFFH
3FFFFFH
, PJ0:
TMP92CH21
2009-06-19
SRLLB
CS1
for