IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 98

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

8–4
Table 8–3. Additional Options (Part 2 of 2)
Table 8–4. PMA Analog Options (Part 1 of 2)
Altera Transceiver PHY IP Core User Guide
PLL type
Starting channel number
Note to
(1) For more information refer to the “FPGA Fabric-Transceiver Interface Clocking” section in the
TX termination resistance
Select the transmitter VOD
control setting
Pre-emphasis pre-tap setting
Enable the pre-emphasis pre-tap
polarity inversion
Select the TX pre-emphasis first
post-tap setting
Specifies the pre-emphasis
second post-tap setting
Enable the pre-emphasis second
post-tap polarity inveresion
Select the receiver common
mode voltage
Table
8–3:
Name
Name
Table 8–4
pre-emphasis. Programmable pre-emphasis boosts high frequencies in the transmit
data signal, which might be attenuated in the transmission media. Using
pre-emphasis can maximize the data opening at the far-end receiver. By applying
pre-emphasis, the high-frequency components are boosted; that is, pre-emphasized.
There are three pre-emphasis taps—pre-tap, first post-tap, and second post-tap. The
pre-tap sets the pre-emphasis on the data bit before the transition. The first post-tap
and second post-tap set the pre-emphasis on the transition bit and the successive bit,
respectively. The pre-tap and second post-tap also provide inversion control. These
settings are only required for Stratix IV GX and GT. These are automatically calculated
for Stratix V GX devices.
describes the Analog Options tab. Many of the analog options control
CMU, ATX
0–96
OCT_85_OHMS
OCT_100_OHMS
OCT_120_OHMS
OCT_150_OHMS
0–7
0–7
On
Off
0–15
0–7
On
Off
TRISTATE
0.82V
1.1v
Parameters for Stratix IV and Derivatives
Value
Value
Allows you to choose a clock multiplier unit (CMU) or auxiliary
transmit (ATX) PLL. The CMU PLL is designed to achieve low TX
channel-to-channel skew. The ATX PLL is designed to improve
jitter performance. This option is only available for Stratix IV GX
devices.
The physical channel number for this transceiver channel.
Indicates the value of the termination resistor for the transmitter.
Sets V
Sets the amount of pre-emphasis on the TX buffer.
Determines whether or not the pre-emphasis control signal for the
pre-tap is inverted. If you turn this option on, the pre-emphasis
control signal is inverted.
Sets the amount of pre-emphasis for the 1st post-tap.
Sets the amount of pre-emphasis for the 2nd post-tap.
Determines whether or not the pre-emphasis control signal for the
second post-tap is inverted. If you turn this option on, the
pre-emphasis control signa is inverted.
Specifes the RX common mode voltage.
OD
for the various TX buffers.
Stratix IV Transceiver Clocking
Description
Description
Chapter 8: Low Latency PHY IP Core
December 2010 Altera Corporation
Parameter Settings
chapter.