IPR-FFT Altera, IPR-FFT Datasheet
IPR-FFT
Specifications of IPR-FFT
Related parts for IPR-FFT
IPR-FFT Summary of contents
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... Innovation Drive San Jose, CA 95134 www.altera.com FFT MegaCore Function User Guide MegaCore Version: Document Date: 10.1 December 2010 ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation ...
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... Mixed Radix-4/2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5 Quad-Output FFT Engine Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5 Single-Output FFT Engine Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6 I/O Data Flow Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6 Streaming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7 Streaming FFT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7 Enabling the Streaming FFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8 © December 2010 Altera Corporation Contents FFT MegaCore Function User Guide ...
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... Block Floating Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1 Calculating Possible Exponent Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2 Implementing Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2 Achieving Unity Gain in an IFFT+FFT Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–4 Additional Information Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2 FFT MegaCore Function User Guide © December 2010 Altera Corporation ...
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... Errata. Altera verifies that the current version of the Quartus previous version of each MegaCore and Errata report any exceptions to this verification. Altera does not verify compilation with MegaCore function versions older than one release. Device Family Support Table 1–2 defines the device support levels for Altera IP cores. ...
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... FFT MegaCore Function User Guide Chapter 1: About This MegaCore Function Support Final Preliminary Preliminary Final Final Final Preliminary Preliminary HardCopy Compilation HardCopy Companion HardCopy Companion HardCopy Companion Final Final Final Final Final Final Preliminary Final © December 2010 Altera Corporation Features ...
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... Parameterization-specific VHDL and Verilog HDL testbench generation ■ Transform direction (FFT/IFFT) specifiable on a per-block basis Easy-to-use IP Toolbench interface ■ IP functional simulation models for use in Altera-supported VHDL and Verilog ■ HDL simulators ■ DSP Builder ready f For information about Avalon-ST interfaces, refer to the ...
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... The transform direction is specifiable on a per-block basis using an input port. MegaCore Verification Before releasing a version of the FFT MegaCore function, Altera runs comprehensive regression tests to verify its quality and correctness. Custom variations of the FFT MegaCore function are generated to exercise its various parameter options, and the resulting simulation models are thoroughly simulated with the results verified against master simulation models ...
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... Points Engines (1) LUTs 256 (2) 1 3129 1024 (2) 1 3234 4096 1 3291 256 (3) 2 5161 1024 (3) 2 5270 © December 2010 Altera Corporation Memory Memory 9 × 9 (Bits) (M9K) Blocks 39168 20 24 155904 20 24 622848 76 24 Logic Memory Memory 9 × 9 Registers (Bits) (M9K) ...
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... Memory 9 × MAX (Bits) (M9K) Blocks (MHz) 14592 8 24 232 57600 8 24 246 © December 2010 Altera Corporation ...
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... Quad Output 4 256 Single Output 1 1024 Single Output 1 4096 Single Output 1 256 Single Output 2 1024 Single Output 2 © December 2010 Altera Corporation Combinational Logic (2) LUTs Registers 3277 4044 5141 5872 5248 6064 5304 6240 9012 10659 9144 10868 9241 11058 ...
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... MAX Clock 18 × Cycle Transform MAX Blocks (MHz) Count Time (μs) 20 341 256 0.75 28 323 1024 3.17 36 320 4096 12.8 48 303 256 0.84 64 286 1024 3.58 80 286 4096 14.33 © December 2010 Altera Corporation ...
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... Block throughput is the minimum number of cycles between two successive start-of-packet (sink_sop) pulses. Table 1–14 lists resource usage with burst data flow architecture, using the 4 multipliers /2 adders complex multiplier structure, for data and twiddle width 16, for Stratix III (EP3SE50F780C2) devices. © December 2010 Altera Corporation Logic Memory Memory Registers ...
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... December 2010 Altera Corporation ...
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... Fixed 256 2517 Fixed 1024 3489 Fixed 4096 4503 Floating 256 18024 Floating 1024 14063 Floating 4096 22030 © December 2010 Altera Corporation Transform Calculation Time (2) Transform Calculation f (MHz) Cycles Time (μs) Cycles max 413 585 1.42 841 402 2652 6.6 ...
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... Block Throughput (3) Time (μs) Cycles Time (μs) 1.11 331 0.75 4.75 1291 2.93 21.98 6157 14.61 0.93 299 0.7 3.85 1163 2.84 17.07 5133 13.07 0.94 283 0.77 3.77 1099 3.04 14.89 4633 12.61 © December 2010 Altera Corporation ...
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... Quad Output 4 1024 Quad Output 4 4096 Quad Output 4 256 Single Output 1 1024 Single Output 1 4096 Single Output 1 © December 2010 Altera Corporation Combinational Logic Memory (2) ALUTs Registers (Bits) 1794 3502 14592 1829 3684 57600 1881 3852 229632 2968 5489 14592 ...
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... Contains the Altera MegaCore IP Library and third-party IP cores. altera Contains the Altera MegaCore IP Library. OpenCore Plus Evaluation With Altera’s free OpenCore Plus evaluation feature, you can perform the following actions: Simulate the behavior of a megafunction (Altera MegaCore function or AMPP ■ ...
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... After you purchase a license, you can request a license file from the Altera website at www.altera.com/licensing and install it on your computer. When you request a license file, Altera emails you a license.dat file. If you do not have Internet access, contact your local Altera representative. ...
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... FFT MegaCore Function User Guide Chapter 1: About This MegaCore Function Installation and Licensing © December 2010 Altera Corporation ...
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... In DSP Builder, a Simulink symbol for the MegaCore function appears in the MegaCore Functions library of the Altera DSP Builder Blockset in the Simulink library browser. You can use the FFT MegaCore function in the MATLAB/Simulink environment by performing the following steps: 1 ...
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... Launch MegaWizard Plug-in Manager from the Tools menu, and select the option to create a new custom megafunction variation Figure 2–1. MegaWizard Plug-In Manager FFT MegaCore Function User Guide DSP Builder User Guide. (Figure © December 2010 Altera Corporation Chapter 2: Getting Started MegaWizard Plug-In Manager Flow ® Memory- Avalon Interface 2–1). ...
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... Figure 2–2. Select the MegaCore Function 7. Click Next to launch IP Toolbench. Parameterize the MegaCore Function To parameterize your MegaCore function, follow these steps: 1. Click Step 1: Parameterize in IP Toolbench © December 2010 Altera Corporation Figure 2–2 shows the wizard after you have (Figure 2–3 on page 2–4). ...
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... Quartus II project and the generated HDL for your MegaCore function variation may be incorrect if this value is changed (Figure 2–4). Figure 2–4. Parameters Tab FFT MegaCore Function User Guide Chapter 2: Getting Started MegaWizard Plug-In Manager Flow © December 2010 Altera Corporation ...
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... Quad Output FFT engine architecture and the minimum number of parallel FFT engines for the required throughput single FFT engine architecture provides enough performance for 1,024-point streaming I/O data flow FFT. © December 2010 Altera Corporation (Figure 2–5). FFT MegaCore Function User Guide 2–5 ...
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... Click the Implementation Options tab Figure 2–6. Implementation Options Tab FFT MegaCore Function User Guide Chapter 2: Getting Started MegaWizard Plug-In Manager Flow where 6 ≤ m ≤ log m (transform length) can be 2 (Figure 2–6). © December 2010 Altera Corporation ...
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... To generate an IP functional simulation model for your MegaCore function, follow these steps: 1. Click Step 2: Set Up Simulation in IP Toolbench 2. Turn on Generate Simulation Model 3. Choose the required language in the Language list. © December 2010 Altera Corporation (Figure 2–3 on page 2–4). (Figure 2–7 on page 2–8). ...
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... The generation phase may take several minutes to complete. The generation progress and status is displayed in a report window. Figure 2–8 FFT MegaCore Function User Guide (Figure 2–3 on page shows the generation report. Chapter 2: Getting Started MegaWizard Plug-In Manager Flow 2–4). © December 2010 Altera Corporation ...
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... December 2010 Altera Corporation describes the generated files and other files that may be in your project (Note 1) & (2) Description The text file contains input imaginary component random data. This file is read by the generated VHDL or Verilog HDL MATLAB testbenches ...
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... Tcl Script that sets up NativeLink in the Quartus II software to natively simulate the design using selected EDA tools. Refer to Simulation Tools Using NativeLink” on page Intel hex-format ROM initialization files (variable streaming FFT only). Chapter 2: Getting Started Simulate the Design “Simulating in Third-Party 2–12. © December 2010 Altera Corporation ...
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... MATLAB software. The model takes a complex vector as input and it outputs the transform-domain complex vector. The lengths and direction of the transforms (FFT/IFFT) (specified as one entry per block) are also passed as an input to the model. © December 2010 Altera Corporation Scaling. 2–11 AN 404: FFT/IFFT Block ...
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... MegaCore function. f For more information about IP functional simulation models, refer to the Altera IP in Third-Party Simulation Tools Handbook. Simulating in Third-Party Simulation Tools Using NativeLink You can perform a simulation in a third-party simulation tool from within the Quartus II software, using NativeLink ...
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... Quartus II software. The .qip file contains the information about the MegaCore function that the Quartus II software requires the Processing menu, click Start Compilation. © December 2010 Altera Corporation chapter in volume 3 of the Quartus II Handbook. 2–13 Simulating Altera IP in Third-Party FFT MegaCore Function User Guide ...
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... On the Processing menu, click Start Compilation. Program a Device After you have compiled your design, program your targeted Altera device, and verify your design in hardware. With Altera's free OpenCore Plus evaluation feature, you can evaluate the FFT MegaCore function before you purchase a license ...
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... A radix-4 decomposition, which divides the input sequence recursively to form four-point sequences, has the advantage that it requires only trivial multiplications in the four-point DFT and is the chosen radix in the Altera FFT MegaCore function. This results in the highest throughput decomposition, while requiring non-trivial complex multiplications in the post-butterfly twiddle-factor rotations only ...
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... To yield uniform scaling across successive output blocks, you must scale the FFT function output by the final exponent comparing the block-floating point output of the Altera FFT MegaCore function to the output of a full precision FFT from a tool like MATLAB, the output should be scaled –exponent_ou to “ ...
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... The Avalon-ST interface inherently synchronizes multi-channel designs, which allows you to achieve efficient, time-multiplexed implementations without having to implement complex control logic. © December 2010 Altera Corporation (4 √2) = 2.5 bits, which is accommodated in the 2 Output Order Mode ...
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... FFT MegaCore Function User Guide (N) stages with each stage containing a single butterfly unit and a Chapter 3: Functional Description FFT Processor Engine Architectures Avalon Interface © December 2010 Altera Corporation ...
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... Figure 3–1. Quad-Output FFT Engine SW x[k,0] RAM A0 RAM x[k,1] A1 RAM x[k,2] A2 RAM A3 x[k,3] © December 2010 Altera Corporation (N)) stages. If transform length is an integral 4 (N) stages are implemented using a radix-4 architecture. 4 (N)) – the stages in a radix-4 architecture, and implements the 4 FFT Engine G[k,0] G[k, ...
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... For information about setting the architectural parameters in IP Toolbench, refer to “Parameterize the MegaCore Function” on page FFT MegaCore Function User Guide G[k,0] FFT Engine -j G[k, G[k, G[k, ROM 2–3. Chapter 3: Functional Description I/O Data Flow Architectures (Figure 3–2 on H[k,m] BFPU RAM © December 2010 Altera Corporation ...
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... Figure 3–4. FFT Streaming Data Flow Architecture Input Flow Control clk reset_n sink_valid sink_ready sink_sop inverse sink_real sink_imag © December 2010 Altera Corporation shows an example simulation waveform. Table 3–4 on page clk EXP0 (3) 3–7 3– ...
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... Table 3–2. fftpts and Transform Size FFT MegaCore Function User Guide [3] 3–7). fftpts 10000000000 01000000000 00100000000 00010000000 00001000000 Chapter 3: Functional Description I/O Data Flow Architectures Figure 3–5 shows [10 [11 [ [10 [11 [12] EXP0 Transform Size 1,024 512 256 128 64 © December 2010 Altera Corporation ...
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... If sink_valid is de-asserted between frames, the data currently in the FFT continues to be processed and transferred to the output. when sink_valid is de-asserted between frames and within a frame. The FFT may optionally be disabled by deasserting the clk_en signal. © December 2010 Altera Corporation Figure 3–6 shows the output flow control when the output order is x0 ...
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... FFT MegaCore Function User Guide Figure 3–9 and 3–11 show the data flow output when the FFT is clk Chapter 3: Functional Description I/O Data Flow Architectures Figure 3–8 © December 2010 Altera Corporation ...
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... On the next clock cycle, sink_sop is de-asserted and the following N – 1 complex input data samples should be loaded in natural order. On the last complex data sample, sink_eop should be asserted. © December 2010 Altera Corporation clk shows an example simulation waveform. -13609 ...
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... For information about enabling the buffered burst FFT, refer to Streaming FFT” on page FFT MegaCore Function User Guide Figure 3–12 shows the input flow control ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( [ [ [ [ [ [ [ [ [ [ [ [5] EXP0 (Figure 3–11). 3–8. © December 2010 Altera Corporation Chapter 3: Functional Description I/O Data Flow Architectures [ [10] “Enabling the ...
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... FFT frame only when the previous transform has been fully unloaded. f For information about enabling the buffered burst FFT, refer to Streaming FFT” on page Parameters Table 3–3 shows the FFT MegaCore function’s parameters. © December 2010 Altera Corporation -47729 -47729 EXP0 EXP1 3–8. 3–13 271 ...
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... The input and output order for data entering and leaving the FFT (variable streaming architecture only). The internal data representation type (variable streaming architecture only), either fixed point with natural bit-growth or single precision floating point. Chapter 3: Functional Description Parameters Description ““Parameters” on page 3–13. Not © December 2010 Altera Corporation ...
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... On or Off Twiddle ROM Distribution 100% M4K to 100% M512 or 100% M9K to 100% MLAB © December 2010 Altera Corporation Value You can implement the complex multiplier structure with four real multipliers and two adders/subtracters, or three multipliers, five adders, and some additional delay elements. ...
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... Imaginary input data, which represents a signed width number of data precision bits. 1 Asserted by the FFT engine when it can accept data not mandatory to provide data to the FFT during ready cycles. Chapter 3: Functional Description Signals Description Avalon Streaming Description Table 3–6): © December 2010 Altera Corporation ...
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... Output log (maximum 2 number of points) © December 2010 Altera Corporation Size data precision Real input data, which represents a signed width number of data precision bits. Indicates the start of the incoming FFT frame. 1 Asserted when data on the data bus is valid. When sink_valid and sink_ready are asserted, a data transfer takes place ...
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... FFT MegaCore Function User Guide Description Inverse FFT calculated if asserted. Only sampled at SOP. Active-high global clock enable input. If de-asserted, the FFT is disabled. Table 3–6 defines the behavior of the FFT when an incorrect Description Chapter 3: Functional Description Signals © December 2010 Altera Corporation ...
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... Each data sample now shares the same exponent value and data bit width the next core engine. The same core engine can be reused without incurring the expense of a larger engine to accommodate the bit growth. © December 2010 Altera Corporation A. Block Floating Point Scaling function uses block-floating-point (BFP) arithmetic internally to ® ...
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... A–1). For example, for a 16-bit data, 256-point Quad Appendix A: Block Floating Point Scaling Calculating Possible Exponent Values Quad Output Engine (2) Max (2) Min (2) –8 –4 1 –10 –2 0 –11 –3 2 –13 –1 1 –14 –2 3 – –17 –1 4 – –20 0 © December 2010 Altera Corporation ...
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... If the full scale data is not used (or just the MSBs), you must saturate the data to avoid wraparound problems. © December 2010 Altera Corporation full_range_real_out[26:0] <= {real_in[15:0],11'b0}; full_range_imag_out[26:0] <= {imag_in[15:0],11'b0}; full_range_real_out[26] <= {real_in[15]}; ...
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... However, in BFP arithmetic, special attention must be paid to the exponent values of the IFFT/FFT blocks to achieve the unity gain. This section explains the steps required to derive a unity gain output from an Altera IFFT/FFT MegaCore pair, using BFP arithmetic. Because BFP arithmetic does not provide an input for the exponent, you must keep ...
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... The resolution required to accommodate this bit width will, in most cases, exceed the maximum data width supported by the core. f For more information, refer to the Achieving Unity Gain in Block Floating Point IFFT+FFT Pair design example under DSP Design Examples at www.altera.com. © December 2010 Altera Corporation IFFT FFT ...
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... A–6 FFT MegaCore Function User Guide Appendix A: Block Floating Point Scaling Achieving Unity Gain in an IFFT+FFT Pair © December 2010 Altera Corporation ...
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... Contact Technical support Technical training Product literature Non-technical support (General) (Software Licensing) Note: (1) You can also contact your local Altera sales office or sales representative. © December 2010 Altera Corporation Additional Information Changes Made sink_valid products, refer to the following ® Contact ...
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... A warning calls attention to a condition or possible situation that can cause you injury. The angled arrow instructs you to press the enter key. The feet direct you to more information about a particular topic. Additional Information Typographic Conventions © December 2010 Altera Corporation ...