IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 45

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: XAUI PHY IP Core
Interfaces
Table 4–9. XAUI PHY IP Core Registers (Part 4 of 4)
December 2010 Altera Corporation
0x086
0x087
0x088
0x089
0x08a
Word
Addr
[31:8]
[7:4]
[3:0]
[31:16]
[15:8]
[31:8]
[31:3]
[7:0]
[7:4]
[3:0]
[2:0]
Bits
[0]
sticky
sticky
sticky
sticky
R/W
RW
—
—
—
—
R,
R,
R,
R,
Reserved
phase_comp_fifo_error[3:
0]
rlv[3:0]
Reserved
rmfifodatainserted[7:0]
rmfifodatadeleted[7:0]
Reserved
rmfifoempty[3:0]
rmfifofull[3:0]
Reserved
phase_comp_fifo_error[2:
0]
simulation_flag
Register Name
Indicates a RX phase compensation FIFO overflow or
underrun condition on the corresponding lane. Reading the
value of the phase_comp_fifo_error register clears the
bits.
From block: RX phase compensation FIFO.
Indicates a run length violation. Asserted if the number of
consecutive 1s or 0s exceeds the number that was set in the
Runlength check option. Bits 0-3 correspond to lanes 0-3,
respectively. Reading the value of the RLV register clears the
bits.
From block: Word aligner.
When asserted, indicates that the RX rate match block
inserted a ||R|| column. Goes high for one clock cycle per
inserted ||R|| column. Reading the value of the
rmfifodatainserted register clears the bits.
From block: Rate match FIFO.
When asserted, indicates that the rate match block has
deleted an ||R|| column. The flag goes high for one clock
cycle per deleted ||R|| column. There are 2 bits for each
lane. Reading the value of the rmfifodatadeleted
register clears the bits.
From block: Rate match FIFO.
When asserted, indicates that the rate match FIFO is empty
(5 words). Bits 0-3 correspond to lanes 0-3, respectively.
Reading the value of the rmfifoempty register clears the
bits.
From block: Rate match FIFO.
When asserted, indicates that rate match FIFO is full (20
words). Bits 0-3 correspond to lanes 0-3, respectively.
Reading the value of the rmfifofull register clears the
bits.
From block: Rate match FIFO.
Indicates a TX phase compensation FIFO overflow or
underrun condition on the corresponding lane. Reading the
value of the phase_comp_fifo_error register clears the
bits.
From block: TX phase compensation FIFO.
Setting this bit to 1 shortens the duration of reset and loss
timer when simulating. Altera recommends that you keep
this bit set during simulation.
Description
Altera Transceiver PHY IP Core User Guide
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—
—
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4–11