IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 113

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 10: Migrating from Stratix IV to Stratix V
PCI Express PHY (PIPE)
Table 10–4. PCIe PHY (PIPE) Correspondence between Stratix IV GX Device and Stratix V Device Signals (Part 3 of 3)
December 2010 Altera Corporation
rx_locktodata
rx_locktorefclk
tx_invpolarity
rx_errdetect
rx_disperr
rx_patterndetect
tx_phase_comp_fifo_error
rx_phase_comp_fifo_error
rx_signaldetect
rx_rlv
rx_datain
tx_dataout
cal_blk_clk
fixedclk
reconfig_clk
reconfig_togxb
reconfig_fromgxb
Not available
Note to
(1) <n> = the number of lanes. <d> = the total deserialization factor from the pin to the FPGA fabric.
(Note 1)
Stratix IV GX Device Signal Name
Table
10–4:
Avalon MM Management Interface
Refer to the
Interface” on page 6–6
rx_serial_data
tx_serial_data
cal_blk_clk
fixedclk
Refer to the
Interface” on page 6–6
phy_mgmt_clk_reset
phy_mgmt_clk
phy_mgmt_address
phy_mgmt_read
phy_mgmt_readdata
phy_mgmt_write
phy_mgmt_writedata
Reconfiguration
Stratix V Device Signal Name
“Avalon-MM PHY Management
“Avalon-MM PHY Management
Altera Transceiver PHY IP Core User Guide
[<n>-1:0]
[<n>-1:0]
[<n>-1:0]
[(<d>/8)*<n>-1:0]
[(<d>/8)*<n>-1:0]
[(<d>/8)*<n>-1:0]
[<n>-1:0]
[<n>-1:0]
[<n>-1:0]
[<n>-1:0]
[<n>-1:0]
[<n>-1:0]
1
1
1
[3:0]
[16:0]
1
1
[8:0]
1
[31:0]
1
[31:0]
Width
10–7