IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 60

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–8
Table 5–7. Interlaken Registers (Part 3 of 3)
Table 5–8. Serial Interface
Table 5–9. Serial Interface
Altera Transceiver PHY IP Core User Guide
0x081
pll_ref_clk
tx_serial_data
rx_serial_data
Word
Addr
PLL Interface
TX and RX Serial Interface
[31:30]
[23:0]
Signal Name
Signal Name
Bits
[24]
[25]
[26]
[27]
[28]
[29]
Table 5–9
Table 5–9
R/W
—
—
R
R
R
R
R
R
Reserved
rx_word_lock
rx_sync_lock
rx_framing_err
rx_crc32_err
rx_scrm_err
rx_sync_word_err
Reserved
describes the signals in the PLL interface.
describes the signals in the chip-to-chip serial interface.
Register Name
Input
Output
Input
Direction
Direction
Stratix V Device Registers
Reference clock for the PHY PLLs. Refer to the Lane rate entry in
Table 5–3 on page 5–2
Differential high speed serial output data. Using the PCML I/O
standard. Clock is recovered from the data.
Differential high speed serial input data. Using the PCML I/O
standard. Clock is recovered from the data.
Asserted when the first alignment pattern is found. The RX
FIFO generates this synchronous signal.
Asserted by the frame synchronizer to indicate that 4 sync
words have been identified so that the RX metaframe is
synchronized.
From block: Frame synchronizer.
Asserted by the frame synchronizer to indicate an RX
synchronization error.
From block: Frame synchronizer.
Asserted by the CRC32 checker to indicate a CRC error in
the corresponding RX lane.
From block: CRC32 checker.
Asserted by the frame synchronizer to indicate an RX
scrambler mismatch.
From block: Frame synchronizer.
Asserted by the frame synchronizer to indicate that a sync
word is missing.
From block: Frame synchronizer.
for required frequencies.
Description
Description
Description
—
—
December 2010 Altera Corporation
Chapter 5: Interlaken PHY IP Core
Interface