IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 76

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–12
Simulation
Altera Transceiver PHY IP Core User Guide
f
When you generate your PCIe PIPE IP core, the Quartus II software generates the
HDL files that define your parameterized IP core. In addition, the Quartus II software
generates an example Tcl test script to compile and simulate your design.
illustrates the directory structure for the generated files.
Figure 6–5. Directory Structure for Generated Files
If you select VHDL for PCIe PIPE PHY, only the wrapper generated by the Quartus II
software is in VHDL. All the underlying files are written Verilog or System Verilog. To
enable simulation using a VHDL-only ModelSim license, the underlying Verilog and
System Verilog files for the PCIe PIPE PHY are encrypted so that they can be used
with the top-level VHDL wrapper without purchasing a mixed-language simulator.
For more information about simulating with ModelSim, refer to the
ModelSim Support
Altera provides an example Tcl script, modelsim_example_script.tcl, with the PCI
Express PIPE PHY IP core to illustrate how to compile and simulate the core in
ModelSim. You must edit this script to include the following information:
■
■
■
The simulation language
The top-level PCIe PIPE PHY variation name
The name of your testbench
chapter in volume 3 of the Quartus II Handbook.
<project_dir>
<design_name>.v or .vhd - the parameterized PCIe PIPE PHY IP core
<design_name>.qip - lists all files used in the PCIe PIPE PHY IP design
<design_name>.bsf - a block symbol file for you PCIe PIPE PHY IP core
<project_dir>/<design_name> - includes PHY IP Verilog and
System Verilog design files for synthesis
pcie_phy_pipe_assignments.qip = an example of the PLL_TYPE
assignment that assigns the CMU for the TX PLL. To change the
PLL type to LC or ATX, update the PLL_TYPE option to ATX.
<design_name>_sim/altera_pcie_phy = includes plain text
Verilog and System Verilog design files for simulation
modelsim_example_script.tcl = example file for compilation and
<design_name>_sim/alt_pcie_phy/mentor = PHY IP encrypted
Verilog and System Verilog design files for simulation in ModelSim
when using a VHDL-only license
simulation of the PCIe PIPE PHY IP core in ModelSim
Chapter 6: PCI Express PHY (PIPE) IP Core
December 2010 Altera Corporation
Mentor Graphics
Figure 6–5
Simulation