IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 117

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Revision History
December 2010 Altera Corporation
December
2010
December
2010
December
2010
December
2010
December
2010
Date
Version
1.11
1.1
1.1
1.1
1.1
This chapter provides additional information about the document and Altera.
The table below displays the revision history for the chapters in this user guide.
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Corrected frequency range for the phy_mgmt_clk for the Custom PHY IP core in
on page
Added optional reconfig_fromgxb[67:0] to
detail on size of reconfig_fromgxb in
Removed table providing ordering codes for the Interlaken PHY IP core. Ordering codes are
not required for Stratix V devices using the hard implementation of the Interlaken PHY.
Added note to 10GBASE-R release information table stating that “No ordering codes or
license files are required for Stratix V devices.”
Revised reset diagram.
Added block diagram for reset
Removed support for SOPC Builder
Removed description of SOPC Builder design flow. SOPC Builder is not supported in this
release.
Added Stratix V support
Changed phy_mgmt_address from 16 to 9 bits.
Renamed management interface, adding phy_ prefix
Renamed block_lock and hi_ber signals rx_block_lock and rx_hi_ber, respectively.
Added top-level signals for external PMA and reconfiguration controller in Stratix IV devices.
Refer to
Removed the mgmt_burstcount signal.
Changed register map to show word addresses instead of a byte offset from a base address.
Added support for Arria II GX and Cyclone IV GX with hard PCS
Renamed management interface, adding phy_ prefix
Changed phy_mgmt_address from 16 to 9 bits.
Renamed many signals. Refer to
page 4–5
Changed register map to show word addresses instead of a byte offset from a base address.
Removed the rx_ctrldetect and rx_freqlocked signals.
7–11.
Table 3–14 on page
and
“XAUI Top-Level Signals–Hard IP PCS and PMA” on page 4–6
10GBASE-R PHY Transceiver
XAUI PHY Transceiver
Getting Started
Introduction
3–13.
“XAUI Top-Level Signals—Soft PCS and Hard PMA” on
Changes Made
Table 4–11 on page 4–12
Figure 4–3 on page
Additional Information
Altera Transceiver PHY IP Core User Guide
4–5. Provided more
as appropriate.
Table 7–11
SPR