IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 57

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: Interlaken PHY IP Core
Interface
Table 5–4. Avalon-ST TX Signals
Table 5–5. Avalon-ST RX Signals
December 2010 Altera Corporation
tx_clkout
tx_user_clkout
rx_parallel_data<n>[63:0]
rx_parallel_data<n>[64]
rx_parallel_data<n>[65]
rx_parallel_data<n>[66]
rx_parallel_data<n>[67]
rx_parallel_data<n>[68]
rx_parallel_data<n>[69]
rx_parallel_data<n>[70]
rx_parallel_data<n>[71]
rx_ready
rx_clkout
rx_fifo_clr<n>
rx_dataout_bp<n>
rx_user_clkout
Signal Name
Avalon-ST RX Interface
Signal Name
Table 5–5
Direction
describes the signals in the Avalon-ST RX interface.
Output
Output
Direction
Source
Source
Source
Source
Source
Source
Source
Source
Source
Source
Output
Output
Input
Sink
Output clock from the PCS.
Master channel tx_clkout is available when you do not create the optional
tx_coreclkin.
Avalon-ST data driven from the PCS to the FPGA fabric.
When asserted, indicates that rx_dataout[63:0]is valid.
Indicates whether rx_dataout[63:0] represents command or
data. When 0, rx_dataout[63:0]is data. When 1,
rx_dataout[63:0] is control.
This is a strobe specifying that the current data word is a
synchronization word. It is used for metaframe validation.
When asserted, indicates that the RX FIFO is full.
When asserted, indicates that the RX FIFO can accept new data.
When asserted, indicates that the RX synchronization state machine
has locked to a single synchronization word. The synchronization
state machine must lock to 4, consecutive synchronization words to
exit the synchronization state. This signal is optional.
When asserted, indicates that the RX synchronization state machine
has received 4 consecutive, valid synchronization words. This signal
is optional.
When asserted, indicates a CRC32 error. This signal is optional.
When asserted, indicates that the RX interface has exited the reset
state.
Output clock from the TX PCS.
When asserted, the RX FIFO is flushed. This signal allows you to
clear the FIFO if synchronization is not achieved.
When asserted, enables data transmission. This signal functions as a
read enable. The RX interface has a ready latency of 1 cycle so that
rx_dataout<n>[63:0] and rx_ctrlout are valid the cycle after
rx_dataout_bp<n> is asserted.
Master channel rx_clkout is available when you do not create the
optional rx_coreclkin.
Description
Description
Altera Transceiver PHY IP Core User Guide
5–5