IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 115

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 10: Migrating from Stratix IV to Stratix V
Custom PHY
Table 10–6. Custom PHY Correspondences between Stratix IV GX Device and Stratix V Device Signals
December 2010 Altera Corporation
pll_inclk
tx_datain
tx_ctrlenable
rx_ctrldetect
rx_dataout
rx_runningdisp
rx_enabyteord
rx_datain
tx_dataout
rx_freqlocked
Note to
(1) <n> = the number of lanes. <d> = the total deserialization factor from the pin to the FPGA fabric.
Table
Port Differences
Not available
ALTGX
10–6:
Table 10–4
Stratix V GX/GS devices.
phy_mgmt_clk_reset
phy_mgmt_clk
phy_mgmt_address
phy_mgmt_read
phy_mgmt_readdata
phy_mgmt_write
phy_mgmt_writedata
pll_ref_clk
tx_parallel_data
tx_datak
rx_datak
rx_parallel_data
rx_runningdisp
rx_enabyteord
rx_serial_data
tx_serial_data
rx_is_lockedtodata
lists the differences between the top-level signals in Stratix IV GX and
Avalon MM Management Interface
Avalon-ST Tx Interface
Avalon-ST Rx Interface
High Speed Serial I/O
Custom PHY
Clocks
1
1
8
1
32
1
32
[<p>-1:0]
[<d><n>-1:0]
[<d><n>-1:0]
[<d><n>-1:0]
[<d><n>-1:0]
[<d/8><n>-1:0]
[<n>-1:0]
[<n>-1:0]
[<n>-1:0]
[<n>-1:0]
Altera Transceiver PHY IP Core User Guide
Width
10–9