IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 118

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Info–2
Altera Transceiver PHY IP Core User Guide
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Added simulation support in ModelSim SE, Synopsys VCS MX, Cadence NCSim
Changed number of lanes supported from 4–24 to 1–24.
Changed reference clock to be 1/20th rather than 1/10th the lane rate.
Renamed management interface, adding phy_ prefix
Changed phy_mgmt_address from 16 to 9 bits.
Changed many signal names, refer to
show word addresses instead of a byte offset from a base address.
Added simulation support in ModelSim SE
Added PIPE low latency configuration option
Changed phy_mgmt_address from 16 to 9 bits.
Changed register map to show word addresses instead of a byte offset from a base address.
Added tx_ready, rx_ready, pipe_txswing, and pipe_rxeleciidle signals
Added rx_errdetect, rx_disperr, and rx_a1a2sizeout register fields
Added support for 8B/10B encoding and decoding in Stratix V devices
Added support for rate matching in Stratix V devices.
Added support for Arria II GX, Arria II GZ, HardCopy IV GX, and Stratix IV GX devices
Renamed management interface, adding phy_ prefix
Changed phy_mgmt_address from 8 to 9 bits.
Added many optional status ports and renamed some signals. Refer to
page 7–8
Changed register map to show word addresses instead of a byte offset from a base address.
Renamed management interface, adding phy_ prefix
Changed phy_mgmt_address from 16 to 9 bits.
Changed register map to show word addresses instead of a byte offset from a base address.
Removed rx_offset_cancellation_done signal. Internal reset logic determines when
offset cancellation has completed.
Removed support for Stratix IV GX devices.
Reconfiguration is now integrated into the XAUI PHY IP core and 10GBASE-R PHY IP core.
Revised register map to show word addresses instead of a byte offset from a base address.
Changed phy_mgmt_address from 16 to 9 bits.
and subsequent signal descriptions.
Transceiver Reconfiguration Controller
Migrating from Stratix IV to Stratix V
Interlaken PHY Transceiver
Low Latency PHY IP Core
Custom PHY Transceiver
PCI Express PHY (PIPE)
Changes Made
Figure 5–2 on page
5–4.Changed register map to
December 2010 Altera Corporation
Figure 7–4 on
Additional Information
Revision History
SPR