IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 69

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: PCI Express PHY (PIPE) IP Core
Interfaces
Figure 6–3. PCI Express PIPE IP Core
Note to
(1) Blocks in gray are soft logic. Blocks in white are hard logic.
December 2010 Altera Corporation
Interconnect
Figure
System
Fabric
Tx Data, Datak
6–3:
PIPE Control
PIPE reset
Clocks
Figure 6–3
PCI Express PIPE and Avalon-MM Control Interface for Non-PIPE Functionality
S
Avalon-MM
illustrates the internal modules of the PCI Express PHY (PIPE) IP core.
Mgmt
PHY
(Note 1)
Interconnect
System
Fabric
M
S
S
S
Reconfiguration
Controller
Avalon-MM
Avalon-MM
Transceiver
Non-PIPE
Non-PIPE
Reset
Controller
Control
Status
Non-PIPE
Status
Dynamic
Partial
Reconfiguration
Reset
Clocks
Tx Data, Datak
PIPE Control
Non-PIPE
Control
Altera Transceiver PHY IP Core User Guide
Hard PCS and PMA
PCI Express PIPE
Rx Data, Datak
PIPE Status
Clocks
Valid
6–5