IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 32

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–14
Table 3–13. Transceiver Serial Interface
Table 3–14. External PMA and Reconfiguration Signals
TimeQuest Timing Constraints
Altera Transceiver PHY IP Core User Guide
rx_serial_data<n>
tx_serial_data<n>
Note to
(1) <n> is the channel number
gxb_pdn
pll_locked
pll_pdn
cal_blk_pdn
rx_oc_busy
cal_blk_clk
reconfig_to_gxb[3:0]
reconfig_from_gxb[16:0]
Table
Signal Name
Serial Interface
External PMA Control and Reconfig Interface
Signal Name
3–13:
h
Table 3–13
Table 3–14
the configuration includes external modules for PMA control and reconfiguration.
You enable this configuration by turning on Use external PMA control and reconfig
available for Stratix IV GT devices. This configuration is illlustrated in
page
The timing constraints for Stratix IV GX designs are in alt_10gbaser_phy.sdc. If your
design does not meet timing with these constraints, use LogicLock
alt_10gbaser_pcs block. You can also apply LogicLock to the alt_10gbaser_pcs and
slightly expand the lock region to meet timing.
For more information about LogicLock, refer to
Help.
3–1.
describes the input and outputs of the transceiver.
Direction
describes the additional top-level signals 10GBASE-R PHY IP core when
Output
Direction
Input
Output
Output
Output
Input
Input
Input
Input
Input
(Note 1)
Receiver input data
Transmitter output data
When asserted, powers down the entire GX block. Active high.
When asserted, indicates that the PLL is locked. Active high.
When asserted, powers down the TX PLL. Active high.
When asserted, powers down the calibration block. Active high.
When asserted, indicates offset cancellation is in progress. The
transceiver must remain in reset until offset cancellation completes.
Active high.
Calibration clock. For Stratix IV devices only. It must be in the range
37.5–50 MHz. You can use the same clock for the phy_mgmt_clk and
the cal_blk_clk.
Reconfiguration signals from the transceiver reconfiguration controller
to the PHY device. This signal is only available in Stratix IV devices.
Reconfiguration RAM. The PHY device drives this RAM data to the
transceiver reconfiguration IP.
About LogicLock Regions
Description
Description
Chapter 3: 10GBASE-R PHY IP Core
December 2010 Altera Corporation
TimeQuest Timing Constraints
TM
for the
Figure 3–1 on
in Quartus II