IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 102

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

8–8
Table 8–8. Serial Data Interface
Table 8–9. Optional Status Interface
Altera Transceiver PHY IP Core User Guide
rx_serial_data[<n-1>:0]
tx_serial_data [<n-1>:0]
Note to
(1) <n> is the number of modules connecting to the Transceiver Reconfiguration IP core.
rx_clkout[<n-1>:0]
rx_is_lockedtodata[<n-1>:0]
rx_is_lockedtoref[<n-1>:0]
pll_locked[<n-1>:0]
tx_coreclkin[<n-1>:0]
rx_coreclkin[<n-1>:0]
tx_bitslip
Note to
(1) <n> is the number of modules connecting to the Transceiver Reconfiguration IP core.
Table
Table
Serial Data Interface
Optional Status Interface
8–8:
8–9:
Signal Name
Signal Name
Table 8–8
Table 8–9
describes the signals that comprise the serial data interface.
describes the signals that comprise the optional status interface.
Direction
Direction
Source
Output
Output
Output
Output
Output
Input
Input
Sink
Differential high speed input serial data.
Differential high speed output serial data.
Low speed clock recovered from the serial data.
When asserted, indicates that the RX CDR is locked to
incoming data. This signal is optional. If latency is not critical,
you can read the value of this signal from the
Rx_is_lockedtodata register.
When asserted, indicates that the RX CDR is locked to the input
reference clock. This signal is optional. When the RX CDR is
locked to data, you can ignore transitions on this signal. If
latency is not critical, you can read the value of this signal from
the Rx_is_lockedtoref register.
When asserted, indicates that the TX PLL is locked to the input
reference clock. This signal is asynchronous.
This is an optional clock to drive the write side of the TX PCS
FIFO.
This is an optional clock to drive the read side of the RX PCS
FIFO.
When set, the data sent to the PMA is slipped. The maximum
number of bits that can be slipped is equal to the value selected
in the serialization factor field - 1 or <d> -1.
Description
Description
Chapter 8: Low Latency PHY IP Core
December 2010 Altera Corporation
Interfaces