IPR-ASI Altera, IPR-ASI Datasheet
IPR-ASI
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IPR-ASI Summary of contents
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... Asynchronous Serial Interface (ASI) MegaCore Function User Guide Asynchronous Serial Interface (ASI) MegaCore Function 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-ASI0106-10.1 Document last updated for Altera Complete Design Suite version: Document publication date: User Guide 10.1 January 2011 Subscribe ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... Deserializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 GX Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 Oversampling Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 Word Aligner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 8B10B Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4 Synchronization State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4 Packet Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4 Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5 Appendix A. Constraints Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1 January 2011 Altera Corporation Asynchronous Serial Interface (ASI) MegaCore Function User Guide Contents ...
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... Cyclone Devices Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–5 Classic Timing Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–5 TimeQuest Timing Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–6 Additional Information Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2 Asynchronous Serial Interface (ASI) MegaCore Function User Guide ContentsContents January 2011 Altera Corporation ...
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... Altera does not verify compilation with MegaCore function versions older than one release. Device Family Support The MegaCore functions provide either final or preliminary support for target Altera device families: ■ Final support means the core is verified with final timing models for this device family ...
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... EP4CGX30F484 pin package) devices. (4) Stratix IV GT only supports soft logic mode. Features This section summarizes the features of the ASI MegaCore function. ■ IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators ■ Easy-to-use MegaWizard ■ SOPC Builder ready Support for OpenCore Plus evaluation ■ ...
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... Chapter 1: About This MegaCore Function MegaCore Verification f For information on ASI MegaCore function demonstration on the Altera Cyclone Video Demonstration Board, refer to the MegaCore Verification The ASI MegaCore verification involves the testing of the DVB-ASI specification EN 50083-9 from CENELEC / December 2002 “Cable networks for television signals, sound signals and interactive services. Part 9: Interfaces for CATV/SMATV head-ends and similar professional equipment for DVB/MPEG2 transport streams” ...
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... You need to obtain a license for the MegaCore function only when you are completely satisfied with its functionality and performance, and want to take your design to production. After you obtain a license for ASI, you can request a license file from the Altera web site at www.altera.com/licensing license file, Altera emails you a license ...
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... Chapter 1: About This MegaCore Function Installation and Licensing OpenCore Plus Evaluation With Altera’s free OpenCore Plus evaluation feature, you can perform the following actions: ■ Simulate the behavior of a megafunction (Altera MegaCore function or AMPP megafunction) within your system ■ Verify the functionality of your design, as well as evaluate its size and speed ...
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... Asynchronous Serial Interface (ASI) MegaCore Function User Guide Chapter 1: About This MegaCore Function Installation and Licensing January 2011 Altera Corporation ...
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... Select Flow You can parameterize the ASI MegaCore function using either one of the following flows: SOPC Builder flow ■ ■ MegaWizard Plug-In Manager flow January 2011 Altera Corporation Select Design Flow MegaWizard Plug-In Manager Flow Specify Parameters Simulate with Testbench Instantiate Core ...
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... Asynchronous Serial Interface (ASI) MegaCore Function User Guide SOPC Builder Flow Parameterize the ASI MegaCore function to ■ create a variant that you can instantiate manually in your design 3–1. Chapter 2: Getting Started SOPC Builder Flow MegaWizard Plug-In Manager Flow volume 4 of the Quartus II “Parameter Settings” on January 2011 Altera Corporation ...
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... During system generation, SOPC Builder optionally generates a simulation model and testbench for the entire system, which you can use to easily simulate your system in any of Altera's supported simulation tools. SOPC Builder also generates a set of ModelSim Tcl scripts and macros that you can use to compile the testbench, IP functional simulation models and plain-text RTL design files that describe your system in the ModelSim simulation software ...
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... MegaCore function. 8. After you review the generation report, click Exit to close the MegaWizard Plug-In Manager. Asynchronous Serial Interface (ASI) MegaCore Function User Guide 3–1. Table 2–2. Chapter 2: Getting Started MegaWizard Plug-In Manager Flow “Parameter January 2011 Altera Corporation ...
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... Simulate with IP Functional Simulation Models You can simulate your design using the MegaWizard-generated VHDL and Verilog HDL IP functional simulation models. You can use the IP functional simulation model with any Altera-supported VHDL or Verilog HDL simulator. To use the IP functional simulation model, create a suitable testbench. ...
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... Quartus II software, using NativeLink. f For more information on NativeLink, refer to the Simulation Tools Altera provides a Quartus II project for use with NativeLink in the ip\asi\simulation\quartus directory. To set up simulation in the Quartus II software using NativeLink, follow these steps the File menu click Open Project. Browse to the ip\asi\simulation\quartus directory ...
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... Compile the Design and Program a Device You can use the Quartus II software to compile your design. Refer to Quartus II Help for instructions on performing compilation. After you have compiled your design, program your targeted Altera device and verify your design in hardware. January 2011 Altera Corporation Asynchronous Serial Interface (ASI) MegaCore Function User Guide 2– ...
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... Asynchronous Serial Interface (ASI) MegaCore Function User Guide Chapter 2: Getting Started Compile the Design and Program a Device January 2011 Altera Corporation ...
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... You can change the page that the MegaWizard Plug-In Manager displays by clicking Next or Back at the bottom of the dialog box. You can move directly to a named page by clicking the Parameter Settings, EDA, or Summary tab. January 2011 Altera Corporation 3. Parameter Settings Range Shows the device family that you chose in your Quartus II project ...
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... Asynchronous Serial Interface (ASI) MegaCore Function User Guide Chapter 3: Parameter Settings January 2011 Altera Corporation ...
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... DVB-ASI EN50083-9 standard. A control code input inserts comma characters (K28.5) when no data is available at the input of the encoder. Transceiver The transceiver can be either a serializer for soft-logic implementations transceivers. January 2011 Altera Corporation 4. Functional Description Transceiver 10 Serializer 10 FIFO ...
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... Asynchronous Serial Interface (ASI) MegaCore Function User Guide Handbook; and for more information on the Stratix GX transceiver, Handbook. Protocol Blocks Word 8B10B Aligner Decoder Chapter 4: Functional Description Receiver Stratix IV Device Parallel Sync. Packet Data FSM Sync. Out January 2011 Altera Corporation ...
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... The word aligner is consistently looking for two consecutive comma characters (K28.5) in the parallel data stream coming out of the over-sampling interface. The word-aligner computes the matching position and shifts words accordingly. January 2011 Altera Corporation A–1. Handbook; and for more information on the Stratix GX transceiver, Handbook ...
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... Asynchronous Serial Interface (ASI) MegaCore Function User Guide SYNC_REQ 1 ! CODE_ERROR and KCODE_FOUND SYNC_REQ 2 ! CODE_ERROR and KCODE_FOUND ! CODE_ERROR IN_SYNC 1 ! CODE_ERROR IN_SYNC 2 ! CODE_ERROR IN_SYNC 3 ! CODE_ERROR IN_SYNC 4 Chapter 4: Functional Description Receiver Figure 4–3 shows the CODE_ERROR January 2011 Altera Corporation ...
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... January 2011 Altera Corporation Direction Input ASI input. Calibration clock for Arria GX, Stratix II GX, and Stratix IV Input transceiver. Transceiver block reset and power down. This signal of all the instances that are to be combined into a single transceiver block Input must be connected to a single point ...
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... Unlike rx_ts_status[0], this signal is not dependent on the correct packet or synchronization structure of the stream. Output from transmitter protocol block for split Output protocol/transceiver mode. Chapter 4: Functional Description Signals Description January 2011 Altera Corporation ...
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... Specify timing constraints and exceptions. To enter your timing requirements, you can use constraint entry dialog boxes or edit the previously created .sdc file. The following constraints demonstrates how to properly constrain the ASI MegaCore RX and TX targeting Stratix IV device. January 2011 Altera Corporation A. Constraints Asynchronous Serial Interface (ASI) MegaCore Function User Guide ...
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... ASI TX (Soft Transceiver) set_max_delay -from {tx_clk270}] 33.333 Asynchronous Serial Interface (ASI) MegaCore Function User Guide Constrain Design With TimeQuest Timing Analyzer [get_clocks {rx_serial_clk}] [get_clocks {tx_refclk}] -to [get_clocks {rx_serial_clk}] [get_clocks {tx_refclk}] -to Appendix A: Constraints -to [get_clocks [get_clocks -to [get_clocks [get_clocks January 2011 Altera Corporation ...
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... The following code is an example of a constraint, which you can set using the Quartus II Assignment Editor: set_location_assignment PIN_99 -to asi_rx0 set_location_assignment LC_X32_Y17_N0 -to "asi_rx:u_rx0|asi_megacore_top:asi_megacore_top_inst|asi_receive:asi rx_gen.u_rx|serdes_s2p:u_s2p|sample_a[0]" set_location_assignment LC_X33_Y17_N0 -to "asi_rx:u_rx0|asi_megacore_top:asi_megacore_top_inst|asi_receive:asi rx_gen.u_rx|serdes_s2p:u_s2p|sample_b[0]" set_location_assignment LC_X32_Y17_N1 -to "asi_rx:u_rx0|asi_megacore_top:asi_megacore_top_inst|asi_receive:asi rx_gen.u_rx|serdes_s2p:u_s2p|sample_c[0]" set_location_assignment LC_X33_Y17_N1 -to "asi_rx:u_rx0|asi_megacore_top:asi_megacore_top_inst|asi_receive:asi rx_gen.u_rx|serdes_s2p:u_s2p|sample_d[0]" January 2011 Altera Corporation Asynchronous Serial Interface (ASI) MegaCore Function User Guide A–3 ...
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... Setup—1.5 clocks (4.43 ns) from the 337.5-MHz zero degree clock to the 135-MHz clock ■ Hold—zero clocks from the 337.5-MHz clock to the 135-MHz clock Asynchronous Serial Interface (ASI) MegaCore Function User Guide Appendix A: Constraints Constraints For ASI Receivers January 2011 Altera Corporation ...
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... CLOCK_SETTINGS input_refclk -to rx_refclk set_global_assignment -name FMAX_REQUIREMENT "27 MHz" -section_id input_refclk set_instance_assignment -name CLOCK_SETTINGS rxclk -to "u_clkdiv|clkdiv" set_global_assignment -name BASED_ON_CLOCK_SETTINGS input_refclk - section_id rxclk set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 5 -section_id rxclk set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 25 -section_id January 2011 Altera Corporation Asynchronous Serial Interface (ASI) MegaCore Function User Guide A–5 ...
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... MHz" create_generated_clock -divide_by 5 -multiply_by 2 set_max_delay 4.43 -from {u_rx_pll|altpll:altpll_component|_clk0} -to {u_clkdiv|clkdiv} set_min_delay 0 -from {u_rx_pll|altpll:altpll_component|_clk0} -to {u_clkdiv|clkdiv} Asynchronous Serial Interface (ASI) MegaCore Function User Guide -name {rx_refclk} {rx_refclk} -source u_rx_pll|altpll:altpll_component|_clk0 \ -name {u_clkdiv|clkdiv} \ Appendix A: Constraints Constraints For ASI Receivers \ January 2011 Altera Corporation ...
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... To locate the most up-to-date information about Altera products, refer to the following table. Contact Technical support Technical training Product literature Non-technical support (General) (Software Licensing) Note to Table: (1) You can also contact your local Altera sales office or sales representative. January 2011 Altera Corporation Additional Information Changes (1) Contact Method Website www.altera.com/support Website www ...
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... A warning calls attention to a condition or possible situation that can cause you injury. The envelope links to the Email Subscription Management Center website, where you can sign up to receive update notifications for Altera documents. Additional InformationAdditional Information Typographic Conventions page of the Altera January 2011 Altera Corporation ...