IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 85

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 7: Custom PHY IP Core
Parameter Settings
Table 7–6. Rate Match FIFO Options
Table 7–7. Byte Order Options
December 2010 Altera Corporation
Enable rate match FIFO
Rate match
insertion/deletion +ve
disparity pattern
Rate match
insertion/deletion -ve
disparity pattern
Note to
(1) The rate match FIFO is not supported in Stratix V devices.
Enable byte ordering block
Enable byte ordering block
manual control
Byte ordering pattern
Byte ordering pad pattern
Table
Byte Ordering
Name
Name
7–6:
1
If you enable the rate match FIFO, the parameter editor provides options to enter the
rate match insertion and deletion patterns. The lower 10 bits are the control pattern,
and the upper 10 bits are the skip pattern.
Rate Match tab.
The byte ordering block is available when the PCS width is doubled at the byte
deserializer. Byte ordering identifies the first byte of a packet by determining whether
the programmed start-of-packet (SOP) pattern is present; it inserts enough pad
characters in the data stream to force the SOP to the lowest order byte lane.
describes the byte order options.
You cannot enable Rate Match FIFO when your application requires byte ordering.
Because the rate match function inserts and deletes idle characters, it may shift the
SOP to a different byte lane.
On/Off
1101000011
1010000011
0010111100
0101111100
On/Off
On/Off
11111011
00000000
(Note 1)
Value
Value
Turn this option on, to enable the rate match functionality. Turning
this option on adds the rx_rmfifofull, rxrmfifoempty,
rxrmfifodatainserted, and rx_rmfifodatadeleted status
signals to your PHY.
Enter a 10-bit skip pattern (bits 10–19) and a 10-bit control pattern
(bits 0–9). The skip pattern must have neutral disparity.
Enter a 10-bit skip pattern (bits 10–19) and a 10-bit control pattern
(bits 0–9). The skip pattern must have neutral disparity.
Turn this option on if your application uses serialization to create a
datapath that is larger than 1 symbol. This option is only available if
you use the byte deserializer.
Turn this option on to choose manual control of byte ordering. This
option creates the rx_enabyteord signal. A byte ordering operation
occurs whenever rx_enabyteord is asserted. To perform multiple
byte ordering operations, deassert and reassert rx_enabyteord.
Specifies the pattern that identifies the SOP.
Specifies the pad pattern that is inserted to align the SOP.
Table 7–6
Description
Description
lists the settings available on the
Altera Transceiver PHY IP Core User Guide
Table 7–7
7–7