IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 72

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–8
Table 6–7. PCI Express PHY (PIPE) IP Core Registers (Part 3 of 4)
Altera Transceiver PHY IP Core User Guide
0x081
0x082
0x083
0x084
0x085
Word
Addr
[31:6]
[31:1]
[31:6]
[31:1]
[31:4]
[5:1]
[5:1]
Bits
[0]
[0]
[0]
[0]
[3]
[2]
[1]
[0]
R/W
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
Reserved
rx_bitslipboundary
selectout
rx_phase_comp_fifo_error
Reserved
tx_phase_comp_fifo_error
Reserved
tx_bitslipboundary_selec
t
tx_invpolarity
Reserved
rx_invpolarity
Reserved
rx_bitslip
rx_bytereversal_enable
rx_bitreversal_enable
rx_enapatternalign
Register Name
Records the number of bits slipped by the RX Word Aligner
to achieve word alignment. Used for very latency sensitive
protocols.
From block: Word aligner.
When set, indicates an RX phase compensation FIFO error.
From block: RX phase compensation FIFO.
When set, indicates a TX phase compensation FIFO error.
From block: TX phase compensation FIFO.
Records the number of bits slipped by the TX bit slipper in
the TX serial output. Used for very latency sensitive
protocols.
From block: TX bit-slipper.
When set, the TX channel inverts the polarity of the TX data.
To block: Serializer.
When set, the RX channel inverts the polarity of the received
data. The 8B/10B decoder inverts the decoder input sample
and then decodes the inverted samples.
To block: 8B/10B decoder.
When set, the word alignment logic operates in bitslip
mode. Every time this register transitions from 0 to 1, the
RX data slips a single bit.
To block: Word aligner.
When set enables byte reversal on the RX interface.
To block: Word aligner.
When set enables bit reversal on the RX interface.
To block: Word aligner.
When set, the word alignment logic operates in pattern
detect mode.
To block: Word aligner.
Chapter 6: PCI Express PHY (PIPE) IP Core
Description
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December 2010 Altera Corporation
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