IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 93

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 7: Custom PHY IP Core
Interfaces
Table 7–15. Serial Interface and Status Signals (Part 2 of 2)
Table 7–16. Reconfiguration Interface
December 2010 Altera Corporation
rx_bitslipboundaryselectout
[<n>-1:0]
Note to
(1) <n> is the number of lanes. <d> is the deserialization factor. <s> is the symbol size in bits. <p> is the number of PLLs.
reconfig_togxb [3:0]
reconfig_fromgxb [16:0]
Table
Dynamic Partial Reconfiguration I/O Interface
Signal Name
7–14:
Signal Name
As silicon progresses towards smaller process nodes, circuit performance is affected
more by variations due to process, voltage, and temperature. These process variations
result in analog voltages that can be offset from required ranges. The calibration
performed by the dynamic reconfiguration interface compensates for variations due
to process, voltage and temperature.
reconfiguration interface. This interface uses the Avalon-MM PHY Management
interface clock.
Direction
Source
Sink
Direction
Output
Reconfiguration signals from the Transceiver Reconfiguration
Controller.
Reconfiguration signals to the Transceiver Reconfiguration Controller.
This signal is used for bit slip word alignment mode. It reports
the number of bits that the RX block slipped to achieve a
deterministic latency.
(Note 1)
Table 7–16
describes the signals in the
Description
Signal Name
Altera Transceiver PHY IP Core User Guide
7–15