IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 29

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 3: 10GBASE-R PHY IP Core
Interfaces
Table 3–10. 10GBASE-R Register Descriptions (Part 3 of 3)
Table 3–11. Status Outputs
December 2010 Altera Corporation
0x083
block_lock
hi_ber
Word
Addr
Signal Name
[5:0]
[7:0]
Status Interface
Clocks, Reset, and Powerdown
Bit
R
R
R/W
Table 3–11
The phy_mgmt_clk_reset signal is the global reset that resets the entire PHY. A
positive edge on this signal triggers a reset.
Refer to the
Handbook for additional information about reset sequences in Stratix IV devices.
BER_COUNT
ERROR_BLOCK_COUNT
Direction
Output
Output
describes signals that provide status information.
Reset Control and Power Down
Name
Asserted to indicate that the block synchronizer has established synchronization.
Asserted by the BER monitor block to indicate a high bit error rate.
Records the bit error rate (BER). Not available for Stratix V
devices.
From block: BER monitor
Records the number of blocks that contain errors. Not
available for Stratix V devices.
From Block: Block synchronizer
chapter in volume 2 of the Stratix IV Device
Description
Description
Altera Transceiver PHY IP Core User Guide
3–11