IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 100

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

8–6
Figure 8–3. PMA
Table 8–5. Avalon-ST interface
Altera Transceiver PHY IP Core User Guide
tx_parallel_data<n>[<d-1>:0]
tx_clkout[<n>-1:0]
tx_ready[<n-1>:0]
rx_parallel_data<n><d-1>:0]
rx_ready[<n-1>:0]
to Embedded
Controller
Avalon-ST TX and RX Data Interface to the MAC
Signal Name
S
Figure 8–3
The following sections describe each interface.
Table 8–5
from the point of view of the MAC so that the TX interface is an Avalon-ST sink
interface and the RX interface is an Avalon-ST source.
Avalon-MM
Mgmt
PHY
Avalon-MM
Control
M
describes the signals in the Avalon-ST interface. These signals are named
shows the interface connectivity of the PMA IP core.
Direction
Source
Output
Output
Output
Sink
to MAC
S
S
Reconfiguration
PHY Controller
This is TX parallel data driven from the MAC FPGA fabric. The ready
latency on this interface is 0, so that the PCS in Low-Latency Bypass
Mode or the MAC in PMA Direct mode must be able to accept data as
soon as it comes out of reset.
This is the clock for TX parallel data.
When asserted, indicates that the Low Latency IP core is ready to
receive data from the MAC. This signal is only used in Stratix IV
devices.
This is RX parallel data driven by the Low Latency PHY IP core. Data
driven from this interface is always valid.
This is the ready signal for the RX interface. The ready latency on this
interface is 0, so that the MAC must be able to accept data as soon as
the PMA comes out of reset. This signal is only used in Stratix IV
devices.
Low Latency
Transeiver
Controller
Rx Data
Tx Data
Native PMA
Control
Dynamic
Reconfiguration
Tx Parallel Data
Rx Parallel Data
S
Channel
Control
PMA and Light-Weight PCS
Description
Rx Serial Data
Tx Serial Data
Chapter 8: Low Latency PHY IP Core
December 2010 Altera Corporation
TX PLL
CMU
<n>
<n>
Interfaces