IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 44

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–10
Table 4–9. XAUI PHY IP Core Registers (Part 3 of 4)
Altera Transceiver PHY IP Core User Guide
0x081
0x082
0x083
0x084
0x085
Word
Addr
[7:0]
[31:16]
[15:8]
[7:0]
[31:16]
[31:2]
[31:4]
[31:4]
[15:8]
[3:0]
[3:0]
Bits
[1]
[0]
R/W
RW
RW
RW
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—
—
—
R
R
Reserved
tx_digital reset
rx_digital reset
Reserved
invpolarity[3:0]
Reserved
invpolarity[3:0]
Reserved
syncstatus[7:0]
patterndetect[7:0]
Reserved
disperr[7:0]
errdetect[7:0]
Register Name
XAUI PCS
Resets the TX PCS clock domain.
To block: RX PCS.
Resets the RX PCS clock domain.
To block: TX PCS.
Inverts the polarity of corresponding bit on the RX interface.
Bit 0 maps to lane 0 and so on.
To block: Word aligner.
Inverts the polarity of corresponding bit on the TX interface.
Bit 0 maps to lane 0 and so on.
To block: Serializer.
Records the synchronization status of the corresponding
bit. The RX sync status regsiter has 2 bits per channel for a
total of 8 bits per XAUI link. Reading the value of the
syncstatus register clears the bits.
From block: Word aligner.
When asserted, indicates that the programmed word
alignment pattern has been detected in the current word
boundary. The RX pattern detect signal is 2 bits wide per
channel or 8 bits per XAUI link. Reading the value of the
patterndetect registers clears the bits.
From block: Word aligner.
Indicates that the received 10-bit code or data group has a
disparity error. When set, the corresponding errdetect
bits are also set. There are 2 bits per RX channel for a total
of 8 bits per XAUI link. Reading the value of the errdetect
register clears the bits
From block: 8B/10B decoder.
When set, indicates that a received 10-bit code group has
an 8B/10B code violation or disparity error. It is used along
with disperr to differentiate between a code violation
error, a disparity error, or both. There are 2 bits per RX
channel for a total of 8 bits per XAUI link. Reading the value
of the errdetect register clears the bits.
From block: 8B/10B decoder.
Description
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December 2010 Altera Corporation
Chapter 4: XAUI PHY IP Core
Interfaces