IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 42

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–8
Table 4–8. Avalon-MM PHY Management Interface
Table 4–9. XAUI PHY IP Core Registers (Part 1 of 4)
Altera Transceiver PHY IP Core User Guide
phy_mgmt_clk
phy_mgmt_clk_reset
phy_mgmt_addr[8:0]
phy_mgmt_writedata[31:0]
phy_mgmt_readdata[31:0]
phy_mgmt_write
phy_mgmt_read
phy_mgmt_waitrequest
0x021
0x022
0x041
Word
Addr
Avalon-MM Interface
[31:0]
[31:0]
[31:0]
Bits
Signal Name
f
The Avalon-MM PHY management block includes master and slave interfaces. This
component acts as a bridge. It transfers commands received on its Avalon-MM slave
interface to its Avalon-MM port. This interface provides access to the PCS and PMA
registers, the Transceiver Reconfiguration, and the Low Latency PHY Controller IP
cores.
Management interface.
For more information about the Avalon-MM interface, including timing diagrams,
refer to the
Register Descriptions
Table 4–9
management interface using word addresses and a 32-bit embedded processor. A
single address space provides access to all registers.
R/W
RW
RW
R
Table 4–8
cal_blk_powerdown
pma_tx_pll_is_locked
reset_ch_bitmask
specifies the registers that you can access using the Avalon-MM PHY
Avalon Interface
Register Name
PMA Common Control and Status Registers
describes the signals that comprise the Avalon-MM PHY
Direction
Output
Output
Input
Input
Input
Input
Input
Input
Reset Control Registers
Avalon-MM clock input.
Global reset signal that resets the entire XAUI PHY. A positive edge
on this signal triggers the reset controller.
9-bit Avalon-MM address.
32-bit input data.
32-bit output data.
Write signal. Asserted high.
Read signal. Asserted high.
When asserted, indicates that the Avalon-MM slave interface is
unable to respond to a read or write request. When asserted, control
signals to the Avalon-MM slave interface must remain constant.
Specifications.
Writing a 1 to channel <n> powers down the calibration
block for channel <n>.
Bit[P] indicates that the TX/CMU PLL (P) is locked to the
input reference clock. There is typically one
pma_tx_pll_is_locked bit per system.
Reset controller channel bitmask for digital resets. The
default value is all 1s. Channel <n> can be reset when
<n> = 1.
Description
Description
December 2010 Altera Corporation
Chapter 4: XAUI PHY IP Core
Interfaces