IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 82

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

7–4
Figure 7–3. Custom PHY with Avalon Interfaces Enabled
Table 7–3. 8B/10B Options
Altera Transceiver PHY IP Core User Guide
Enable 8B/10B decoder/encoder
Enable manual disparity control
Create optional 8B/10B status
port
8B/10B Encoder and Decoder
Name
Figure 7–3
The 8B/10B encoder generates 10-bit code groups (control or data word) with proper
disparity from the 8-bit data and 1-bit control identifier. The 8B/10B decoder receives
10-bit data from the rate matcher and decodes it into an 8-bit data + 1-bit control
identifier.
Table 7–3
shows the top-level interfaces when you disable Avalon data interfaces.
On/Off
On/Off
On/Off
Value
lists the settings available on the 8B/10B tab.
Enable this option if your application requires 8B/10B encoding and
decoding. This option on adds the tx_datak<n>, rx_datak<n>,
and rx_runningdisp<n> signals to your transceiver.
When enabled, you can use the tx_forcedisp signal to control the
disparity of the 8B/10B encoder. Turning this option on adds the
tx_forcedisp and tx_dispval signals to your transceiver.
Enable this option on to include additional 8B/10B the
rx_errdetect and rx_disperr error signals at the top level of the
Custom PHY IP core.
Description
December 2010 Altera Corporation
Chapter 7: Custom PHY IP Core
Parameter Settings