IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 84

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

7–6
Table 7–5. Word Aligner Options
Altera Transceiver PHY IP Core User Guide
Custom
single-width
Custom
double-width
PCIe PIPE PHY
Configuration
Rate Match FIFO
Width (bits)
PMA-PCS
Interface
Table 7–5
The rate match FIFO compensates for small clock frequency differences between the
upstream transmitter and the local receiver clocks by inserting or removing skip
(SKP) symbols or ordered-sets from the inter-packet gap (IPG) or idle streams. It
deletes SKP symbols or ordered-sets when the upstream transmitter reference clock
frequency is greater than the local receiver reference clock frequency. It inserts SKP
symbols or ordered-sets when the local receiver reference clock frequency is greater
than the upstream transmitter reference clock frequency.
10
16
20
10
8
Manual
alignment
Bit-slip
Manual
alignment
Bit-slip
Automatic
synchronized
state machine
Manual
alignment
Bit-slip
Manual
alignment
Bit-slip
Automatic
Synchronized
State Machine
Automatic
synchronized
state machine
provides more information about the word alignment function.
Alignment
Mode
Word
7 and 10 bits
Length (bits)
Alignment
8, 16, 32
8, 16, 32
8, 16, 32
7, 10, 20
Pattern
Word
7, 10
16
16
10
User-controlled signal starts alignment process.
Alignment occurs once unless signal is re-asserted.
User-controlled signal shifts data 1 bit at a time.
User-controlled signal starts alignment process.
Alignment occurs once unless signal is re-asserted.
User-controlled signal shifts data 1 bit at a time.
Data must be 8B/10B encoded and aligns to selected
word aligner pattern.
User-controlled signal starts alignment process.
Alignment occurs once unless signal is re-asserted.
User-controlled signal shifts data 1 bit at a time.
User-controlled signal starts alignment process.
Alignment occurs once unless signal is re-asserted.
User-controlled signal shifts data 1 bit at a time.
Automatically selected word aligner pattern length
and pattern.
Automatically selected word aligner pattern length
and pattern.
Word Alignment Behavior
December 2010 Altera Corporation
Chapter 7: Custom PHY IP Core
Parameter Settings