IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 23

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 3: 10GBASE-R PHY IP Core
Interfaces
Interfaces
Figure 3–3. 10GBASE-R PHY Pinout Showing Interfaces for Both Internal and External Transceivers
December 2010 Altera Corporation
Avalon-MM PHY
Outputs from PCS
Inputs from MAC
SDR XGMII Tx
SDR XGMII Rx
Management
Interface
to MAC
f
1
Figure 3–3
The block diagram shown in the GUI labels the external pins with the interface type
and places the interface name inside the box. The interface type and name are used in
the Hardware Component Description File (_hw.tcl).
For more information about _hw.tcl files, refer to the Component Interface Tcl Reference
chapter in the
The following sections describe the signals in each interface.
xgmii_tx_dc <n> [71:0]
tx_ready
xgmii_tx_clk
xgmii_rx_dc <n> [71:0]
rx_ready
xgmii_rx_clk
phy_mgmt_clk
phy_mgmt_clk_reset
phy_mgmt_addr[15:0]
phy_mgmt_writedata[31:0]
phy_mgmt_readdata[31:0]
phy_mgmt_write
phy_mgmt_read
phy_mgmt_waitrequest
illustrates the top-level signals of the 10Base-R PHY.
SOPC Builder User
10GBASE-R Top-Level Signals
Guide.
reconfig_from_gxb[16:0]
reconfig_to_gxb[3:0]
rx_serial_data <n>
tx_serial_data <n>
rx_block_lock
cal_blk_pdn
rx_oc_busy
cal_blk_clk
pll_ref_clk
pll_locked
rx_hi_ber
gxb_pdn
pll_pdn
Altera Transceiver PHY IP Core User Guide
External PMA and
Reconfiguration
Stratix IV only
Transceiver
Serial Data
Signals for
Status
Clock
f
3–5