IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 89

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 7: Custom PHY IP Core
Interfaces
Table 7–11. Avalon-MM PHY Management Interface
Table 7–12. Low Latency PHY IP Core Registers (Part 1 of 3)
December 2010 Altera Corporation
phy_mgmt_clk
phy_mgmt_clk_reset
phy_mgmt_address[8:0]
phy_mgmt_writedata[31:0]
phy_mgmt_readdata[31:0]
phy_mgmt_write
phy_mgmt_read
0x021
0x022
0x041
0x042
Word
Addr
PHY Management Signals
[31:0]
[31:0]
[31:0]
[1:0]
Bits
Signal Name
R/W
RW
RW
Table 7–11
Register Descriptions
Table 7–12
interface using word addresses and a 32-bit embedded processor. A single address
space provides access to all registers.
W
R
R
cal_blk_powerdown
pma_tx_pll_is_locked
reset_ch_bitmask
reset_control (write)
reset_status(read)
describes the signals in the PHY Management interface.
specifies the registers that you can access over the PHY management
Register Name
PMA Common Control and Status Registers
Direction
Output
Input
Input
Input
Input
Input
Input
Reset Control Registers
Avalon-MM clock input. The frequency range for the
phy_mgmt_clk varies for different devices, as follows:
■
■
Global reset signal. A positive edge on this signal triggers a reset.
9-bit Avalon-MM address.
Input data.
Output data.
Write signal.
Read signal.
Arria II GX, Arria II GZ, HardCopy IV GX, and Stratix IV GX
devices: 37.5–125 MHz
Stratix V devices: 50–150 MHz
Writing a 1 to channel <n> powers down the calibration
block for channel <n>.
Bit[P] indicates that the TX/CMU PLL (P) is locked to the
input reference clock. There is typically one
pma_tx_pll_is_locked bit per system.
Reset controller channel bitmask for digital resets. The
default value is all 1s. Channel <n> can be reset when
<n> = 1.
Writing a 1 to bit 0 initiates a TX digital reset using the reset
controller module. The reset affects channels enabled in the
reset_ch_bitmask. Writing a 1 to bit 1 initiates a RX
digital reset of channels enabled in the
reset_ch_bitmask.
Reading bit 0 returns the status of the reset controller TX
ready bit. Reading bit 1 returns the status of the reset
controller RX ready bit.
Description
Description
Altera Transceiver PHY IP Core User Guide
7–11