IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 30

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–12
Figure 3–4. Stratix IV GT Clock Generation and Distribution
Altera Transceiver PHY IP Core User Guide
10GBASE-R Transceiver Channel - Stratix IV GT
TX
RX
When connected to the hard PMA, the PCS runs at 257.8125 MHz using the
pma_rx_clock provided by the PMA. You must provide the PMA a input reference
clock running at 644.53725MHz to generate the 257.8125 MHz clock.
illustrates the clock generation and distribution for Stratix IV devices.
xgmii_rx_clk
156.25 MHz
xgmii_tx_clk
64
64
RX PCS
(soft IP)
GPLL
TX PCS
(soft IP)
8/33
257.8125
257.8125
40
MHz
40
MHz
(hard IP)
RX PCS
(hard IP)
TX PCS
/2
/2
516.625
516.625
MHz
MHz
20
20
RX PMA
TX PMA
TX PLL
5/4
Gbps serial
Gbps serial
Chapter 3: 10GBASE-R PHY IP Core
December 2010 Altera Corporation
10.3125
644.53125 MHz
10.3125
pll_ref_clk
Figure 3–4
Interfaces