IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 86

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

7–8
Table 7–8. Datapath Options
Interfaces
Figure 7–4. Custom PHY Top-Level Signals
Note to
(1) <n> is the number of lanes. <d> is the deserialization factor. <s> is the symbol size in bits. <p> is the number of PLLs.
Altera Transceiver PHY IP Core User Guide
Deserializer block width
Deserializer actual width
Avalon-MM PHY
Figure
Avalon-ST Rx
Avalon-ST Tx
Management
from MAC
Interface
to MAC
Name
7–4:
Clocks
f
Optional
Optional
Optional
Table 7–8
For a description of the Analog options, refer the to
page
Figure 7–4
8–4.
Auto
Single
Double
Auto
Single
Double
lists the Datapath options.
illustrates the top-level signals of the Custom PHY IP core.
Value
tx_parallel_data[<n><d>-1>:0]
tx_clkout<n>
tx_datak[<n><d>-1:0]
tx_forcedisp[<n><d>-1:0]
tx_dispval[<n><d>-1:0]
rx_parallel_data[<n><d>-1:0]
rx_clkout<n>
rx_datak[<n><d>-1:0]
rx_runningdisp[<n><d>-1:0]
rx_enabyteord[<n>-1:0]
phy_mgmt_clk
phy_mgmt_clk_reset
phy_mgmt_address[8:0]
phy_mgmt_writedata[31:0]
phy_mgmt_readdata[31:0]
phy_mgmt_write
phy_mgmt_read
pll_ref_clk
cal_blk_clk
rx_coreclkin<n>
tx_coreclkin<n>
(Note 1)
Specifies the mode of operation for the deserializer which clocks in
serial input data from the RX buffer using the high-speed recovered
clock and deserializes it using the low-speed parallel recovered clock.
Forwards deserialized data to the RX PCS channel. The following 3
modes are supported:
■
■
■
Specifies the mode selected.
Custom PHY Top-Level Signals
Auto—Instructs the Quartus II software to determine the
appropriate width
Single—supports 8- and 10-bit deserialization factors
Double—supports 16- and 20-bit deserialization factors
rx_bitsilpboundaryselectout[<n>4:0]
tx_bitslipboundaryselect[<n>4:0]
rx_synccstatus[<n>/<d>-1:0]
rx_is_lockedtodata[<n>-1:0]
rx_is_lockedtoref[<n>-1:0]
rx_errdetect[<n>/<d>-1:0]
tx_forceelecidle[<n>-1:0]
rx_signaldetect[<n>-1:0]
rx_disperr[<n>/<d>-1:0]
reconfig_fromgxb[16:0]
reconfig_togxb[3:0]
pll_locked[<p>-1:0]
tx_serial_data<n>
rx_serial_data<n>
Description
“PMA Analog Options” on
rx_ready
rx_bitslip
tx_ready
December 2010 Altera Corporation
Chapter 7: Custom PHY IP Core
High Speed
Reconfiguration
Serial I/O
Transceiver
Interface
Optional
Optional
Status
Interfaces