IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 65

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Figure 6–1. PCI Express PHY (PIPE) with Hard IP PCS and PMA in Stratix V GX Devices
Device Family Support
December 2010 Altera Corporation
PCI Express
MACPHY
from
f
Avalon-ST Tx and Rx
Avalon-ST PIPE
Avalon-ST Reconfig
Avalon-MM Cntrl and Status
The Altera PCI Express PHY (PIPE) IP core implements physical coding sublayer
(PCS) and physical media attachment (PMA) modules as defined by the
Interface for PCI Express (PIPE) Architecture
connects to a PCI Express PHYMAC to create a complete PCI Express design. Altera
supports the Gen1 and Gen2 specifications and ×1, ×2, ×4, or ×8 operation for a total
aggregate bandwidth of 2–32 Gbps.
Figure 6–1
Stratix V GX devices.
For more detailed information about the PCI Express PHY PIPE transceiver channel
datapath, clocking, and channel placement, refer to the “PCI Express” section in the
Handbook.
IP cores provide either final or preliminary support for target Altera device families.
These terms have the following definitions:
■
■
Table 6–1
Altera device families
Table 6–1. Device Family Support
Transceiver Protocol Configurations in Stratix V Devices
Stratix V devices–hard PCS + hard PMA
Other device families
Final support—Verified with final timing models for this device.
Preliminary support—Verified with preliminary timing models for this device.
shows the level of support offered by the PCI Express PIPE IP core for
illustrates the top-level blocks of the PCI Express PHY (PIPE) for
Device Family
Stratix V FPGA
PCI Express PIPE PHY IP Core
Elastic Buffer
Rx Detection
8B/10B
PCS:
6. PCI Express PHY (PIPE) IP Core
specification. The PCI Express PHY (PIPE)
10-bit Interface
Analog Buffers
Preliminary
No support
SERDES
PMA:
chapter of the Stratix V Device
Altera Transceiver PHY IP Core User Guide
Support
Differential PCML
HSSI
Intel PHY
to ASIC,
ASSP,
FPGA