IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 92

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

7–14
Table 7–14. Serial Interface and Status Signals
Table 7–15. Serial Interface and Status Signals (Part 1 of 2)
Altera Transceiver PHY IP Core User Guide
rx_serial_data[<n>-1:0]
tx_serial_data[<n>-1:0]
Note to
(1) <n> is the number of lanes. <d> is the deserialization factor. <s> is the symbol size in bits. <p> is the number of PLLs.
tx_ready
rx_ready
pll_locked[<p>-1:0]
tx_forceelecidle[<n>-1:0]
tx_bitslipboundaryselect
[<n>4:0]
rx_disperr[<d/s><n>-1:0]
rx_errdetect[<d/s><n>-1:0]
rx_syncstatus[<d/s><n>-1:0]
rx_is_lockedtoref[<n>-1:0]
rx_is_lockedtodata[<n>-1:0]
rx_signaldetect[<n>-1:0]
rx_bitslip
Table
Transceiver Serial Data Interface
Optional Status Signals
7–14:
Signal Name
Signal Name
Table 7–14
RX interface.
Table 7–15
describes the differential serial data interface and the status signals for the
describes the optional status signals for the RX interface.
Direction
Direction
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
(Note 1)
Receiver differential serial input data.
Transmitter differential serial output data.
When asserted, indicates that the TX interface is ready to
transmit.
When asserted, indicates that the RX interface is ready to receive.
When asserted, indicates that the PLL is locked to the input
reference clock.
When asserted, enables a circuit to detect a downstream receiver.
It is used for the PCI Express protocol.
This signal is used for bit slip word alignment mode. It selects the
number of bits that the TX block must slip to achieve a
deterministic latency.
When asserted, indicates that the received 10-bit code or data
group has a disparity error.
When asserted, indicates that a received 10-bit code group has
an 8B/10B code violation or disparity error.
Indicates presence or absence of synchronization on the RX
interface. Asserted when word aligner identifies the word
alignment pattern or synchronization code groups in the received
data stream. This signal is optional.
Asserted when the receiver CDR is locked to the input reference
clock. This signal is asynchronous. This signal is optional.
When asserted, the receiver CDR is in to lock-to-data mode.
When deasserted, the receiver CDR lock mode depends on the
rx_locktorefclk signal level. This signal is optional.
Signal threshold detect indicator required for the PCI Express
protocol. When assertied, it indicates that the signal present at
the receiver input buffer is above the programmed signal
detection threshold value.
Used for manual control of bit silpping. The word aligner slips a
bit of the current word for every rising edge of this signal.
(Note 1)
Signal Name
Signal Name
December 2010 Altera Corporation
Chapter 7: Custom PHY IP Core
Interfaces