IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 41

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: XAUI PHY IP Core
Interfaces
Figure 4–5. Interleaved SDR XGMII Data
Table 4–6. SDR TX XGMII Interface
Table 4–7. SDR XGMII Interface
December 2010 Altera Corporation
xgmii_tx_dc[71:0]
xgmii_tx_clk
xgmii_rx_dc[71:0]
xgmii_rx_clk
SDR XGMII RX Interface
Signal Name
Signal Name
Original XGMII Data
[63:56]
[63:56]
This interface runs at 156.25 MHz in accordance with XGMII specification; however,
data is only driven on the rising edge of clock. To meet the bandwidth requirements,
the datapath is eight bytes wide with eight control bits, instead of the standard four
bytes of data and four bits of control. The XAUI IP core treats the datapath as two,
32-bit data buses and includes logic to interleave them, starting with the low-order
bytes.
Table 4–6
Table 4–6
[55:48]
[31:24]
Figure 4–5
describes the signals in the SDR TX XGMII interface.
describes the signals in the SDR RX XGMII interface.
[47:40]
[55:48]
Direction
Direction
illustrates the mapping.
Source
Output
Input
Sink
[39:32]
[23:16]
Contains 4 lanes of data and control for XGMII. Each lane consists of
16 bits of data and 2 bits of control.
■
■
■
■
The XGMII SDR TX clock which runs at 156.25 MHz.
Contains 4 lanes of data and control for XGMII. Each lane consists of
16 bits of data and 2 bits of control.
■
■
■
■
The XGMII SDR RX MAC interface clock which runs at 156.25 MHz.
Interleaved Result
Lane 0–[7:0]/[8], [16:9]/[17]
Lane 1–[25:18]/[26], [34:27]/[35]
Lane 2–[43:36]/[44], [52:45]/[53]
Lane 3–[61:54]/[62],[70:63]/[71]
Lane 0–[7:0]/[8], [16:9]/[17]
Lane 1–[25:18]/[26], [34:27]/[35]
Lane 2–[43:36]/[44], [52:45]/[53]
Lane 3–[61:54]/[62],[70:63]/[71]
[31:24]
[47:40]
[23:16]
[15:8]
Description
Description
[39:32]
[15:8]
Altera Transceiver PHY IP Core User Guide
[7:0]
[7:0]
4–7