IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 87

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 7: Custom PHY IP Core
Interfaces
Table 7–9. Avalon-ST TX Interface
Table 7–10. Avalon-ST RX Interface (Part 1 of 2)
December 2010 Altera Corporation
tx_parallel_data<n>[<d>-1:0]
tx_clkout
tx_datak<n>
tx_forcedisp
tx_dispval
rx_parallel_data[<n><d>-1:0]
rx_clkout
rx_datak<n>
Avalon-ST TX Input Data from the MAC
Avalon-ST RX Output Data to the MAC
Signal Name
Signal Name
f
f
1
The block diagram shown in the GUI labels the external pins with the interface type
and places the interface name inside the box. The interface type and name are used in
the _hw.tcl.
For more information about _hw.tcl files, refer to Component Interface Tcl Reference
chapter in the
The following sections describe the signals in each interface.
Table 7–9
driven from the MAC to the PCS. This is an Avalon sink interface.
For more information about the Avalon-ST protocol, including timing diagrams, refer
to the
Table 7–10
driven from the PCS to the MAC. This is an Avalon source interface.
Avalon Interface
describes the signals in the Avalon-ST input interface. These signals are
describes the signals in the Avalon-ST output interface. These signals are
SOPC Builder User
Direction
Direction
Source
Source
Output
Output
Sink
Sink
Sink
Sink
Specifications.
This is TX parallel data driven from the MAC. The ready latency on this
interface is 0, so that the PHY must be able to accept data as soon as it
comes out of reset.
This is the clock for TX parallel data, control, and status signals.
Data and control indicator for the received data. When 0, indicates that
tx_data is data, when 1, indicates that tx_data is control.
When asserted, this control signal enables disparity to be forced on the
TX channel. This signal is created if you turn On the Enable manual
disparity control option on the 8B/10B tab.
This control signal specifies the disparity of the data. This port is
created if you turn On the Enable disparity control option on the
8B/10B tab.
This is RX parallel data driven from the Custom PHY IP core. The ready
latency on this interface is 0, so that the MAC must be able to accept
data as soon as the PHY comes out of reset. Data driven from this
interface is always valid.
This is the clock for the RX parallel data source interface.
Data and control indicator for the source data. When 0, indicates that
rx_parallel_data is data, when 1, indicates that
rx_parallel_data is control.
Guide.
Description
Description
Altera Transceiver PHY IP Core User Guide
7–9