IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 66

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–2
Resource Utilization
Table 6–2. PCI Express PHY (PIPE) Performance and Resource Utilization—Stratix V Devices
Parameter Settings
Table 6–3. General Options
Altera Transceiver PHY IP Core User Guide
Gen1 ×1
Gen1 ×4
Gen1 ×8
Gen2 ×1
Gen2 ×4
Gen2 ×8
Number of lanes
Protocol version
Deserialization factor
PIPE low latency
synchronous mode
PLL reference clock
frequency
Run length
Enable electrical idle
inferencing
Number of Lanes
Name
Table 6–2
configurations using the current version of the Quartus
Stratix V GX device.
To configure the PCI Express PHY (PIPE) IP core in the parameter editor, click
Installed Plug-Ins > Interfaces > PCI Express > PCI Express PHY (PIPE) v10.1. The
PCI Express PHY PIPE IP core is only available when you select the Stratix V device
family.
This section describes the PCI Express PHY PIPE parameters, which you can set using
the parameter editor.
1, 4, 8
Gen1 (2.5 Gbps)
Gen2 (5.0 Gbps)
8, 16
On/Off
100 MHz
125 MHz
40–160
True/False
Combinational
shows the typical expected device resource utilization for different
ALUTs
Value
460
530
590
460
530
590
Table 6–3
The total number of PCI Express lanes
Specifies the protocol version. Gen1 implements
Specification 1.1.
Specification 2.0.
Specifies the width of the interface between the PHYMAC and PHY
(PIPE). Using the 16-bit interface, reduces the required clock
frequency by half at the expense of extra FPGA resources.
When enabled, the rate match FIFO in low latency mode.
The PIPE standard requires a 100 MHz input clock. The 125 MHz
option is provided as a convenience which, depending on your
design, may reduce the number of clock sources you must generate
on your PCB.
Specifies the legal number of consecutive 0s or 1s.
When True, enables the PIPE interface to infer electrical idle instead
of detecting electrical idle using analog circuitry. For more
information about inferring electrical idle, refer to “Section 4.2.3.4
Inferring Electrical Idle” in the
Logic Registers
lists the settings available on General Options tab.
285
373
425
295
373
425
Gen2 implements
Memory Bits
Description
PCI Express Base Specification 2.0.
0
0
0
0
0
0
Chapter 6: PCI Express PHY (PIPE) IP Core
®
II software targeting a
PCI Express Base
December 2010 Altera Corporation
PCI Express Base
PLLs
Resource Utilization
2
5
9
2
5
9