IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 21

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 3: 10GBASE-R PHY IP Core
Release Information
Release Information
Device Family Support
December 2010 Altera Corporation
f
Table 3–1
Table 3–1. 10GBASE-R Release Information
IP cores provide either final or preliminary support for target Altera device families.
These terms have the following definitions:
■
■
Table 3–2
device families.
Table 3–2. Device Family Support
For speed grade information, refer to “Transceiver Performance Specifications” the
DC and Switching Characteristics
Stratix IV devices or
of the Stratix V Handbook for Stratix V devices.
Version
Release Date
Ordering Codes
Product ID
Vendor ID
Note to
(1) No ordering codes or license files are required for Stratix V devices.
Stratix IV GT devices–soft PCS and hard PMA
Stratix V devices–hard PCS and hard PMA
Other device families
Final support—Verified with final timing models for this device.
Preliminary support—Verified with preliminary timing models for this device.
Figure
provides information about this release of the 10GBASE-R PHY IP core.
shows the level of support offered by the 10GBASE-R IP core for Altera
3–1:
Item
(Note 1)
Device Family
DC and Switching Characteristics for Stratix V Devices
chapter in volume 3 of the Stratix IV Handbook for
IPR-10GBASERPCS (renewal)
IP-10GBASERPCS (primary)
Final
Preliminary
No support
December 2010
Description
Altera Transceiver PHY IP Core User Guide
00D7
6AF7
10.1
Support
in volume 3
3–3