IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 90

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

7–12
Table 7–12. Low Latency PHY IP Core Registers (Part 2 of 3)
Altera Transceiver PHY IP Core User Guide
0x044
0x061
0x063
0x064
0x065
0x066
00x06
7
0x080
0x082
Word
Addr
[31:4,0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:6]
[5:1]
Bits
[1]
[2]
[3]
[0]
R/W
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
R
R
reset_fine_control
reset_tx_digital
reset_rx_analog
reset_rx_digital
phy_serial_loopback
pma_rx_signaldetect
pma_rx_set_locktodata
pma_rx_set_locktoref
pma_rx_is_lockedtodata
pma_rx_is_lockedtoref
Lane or group number
pcs8g_rx_status
rx_phase_comp_fifo_error
rx_bitslipboundaryselect
out
Register Name
PMA Control and Status Registers
Low Latency PCS
You can use the reset_fine_control register to create
your own reset sequence. The reset control module,
illustrated in
reset sequence at power on and whenever the
phy_mgmt_clk_reset is asserted. Bits [31:4, 0] are
reserved.
Writing a 1 causes the internal TX digital reset signal to be
asserted, resetting all channels enabled in
reset_ch_bitmask. You must write a 0 to clear the
reset condition.
Writing a 1 causes the internal RX digital reset signal to be
asserted, resetting the RX analog logic of all channels
enabled in reset_ch_bitmask. You must write a 0 to
clear the reset condition.
Writing a 1 causes the RX digital reset signal to be asserted,
resetting the RX digital channels enabled in
reset_ch_bitmask. You must write a 0 to clear the
reset condition.
Writing a 1 to channel <n> puts channel <n> in serial
loopback mode.
When channel <n> =1, indicates that receive circuit for
channel <n> senses the specified voltage exists at the RX
input buffer. This option is only operational for the PCI
Express PHY IP core.
When set, programs the RX CDR PLL to lock to the
incoming data. Bit <n> corresponds to channel <n>.
When set, programs the RX CDR PLL to lock to the
reference clock. Bit <n> corresponds to channel <n>.
When asserted, indicates that the RX CDR PLL is locked to
the RX data, and that the RX CDR has changed from LTR to
LTD mode. Bit <n> corresponds to channel <n>.
When asserted, indicates that the RX CDR PLL is locked to
the reference clock. Bit <n> corresponds to channel <n>.
Specifies lane or group number for indirect addressing
which is used for all PCS control and status registers. For
variants that stripe data across multiple lanes, this is the
logical group number. For non-bonded applications, this is
the logical lane number.
Reserved.
When set, indicates an RX phase compensation FIFO error.
From block: RX phase Compensation FIFO
This is an output from the bit slip word aligner which shows
the number of bits slipped.
From block: Word aligner.
Figure 1–1 on page
Description
December 2010 Altera Corporation
Chapter 7: Custom PHY IP Core
1–2, performs a standard
Interfaces