IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 39

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: XAUI PHY IP Core
Interfaces
Interfaces
Figure 4–3. XAUI Top-Level Signals—Soft PCS and Hard PMA
December 2010 Altera Corporation
Avalon-MM PHY
Clocks
SDR Rx XGMII
Reset
SDR Tx XGMII
Management
and
Interface
f
1
Optional
Figure 4–3
implementation which is available for Stratix IV GX and Stratix V devices.
illustrates the top-level signals of the XAUI PHY IP core for the hard IP
implementation which is available for Stratix IV GX devices. With the exception of the
optional signals available for debugging, the pinout of the two implementations is
nearly identical.
The block diagram shown in the GUI labels the external pins with the interface type
and places the interface name inside the box. The interface type and name are used to
define component interfaces in the _hw.tcl.
For more information about _hw.tcl files refer to refer to the Component Interface Tcl
Reference chapter in the
xgmii_tx_dc[71:0]
xgmii_tx_clk
xmii_rx_dc[71:0]
xgmii_rx_clk
phy_mgmt_clk
phy_mgmt_clk_reset
phy_mgmt_address[8:0]
phy_mgmt_writedata[31:0]
phy_mgmt_readdata[31:0]
phy_mgmt_write
phy_mgmt_read
phy_mgmt_waitrequest
pll_ref_clk
rx_digitalreset
tx_digitalreset
illustrates the top-level signals of the XAUI PHY IP core for the soft IP
XAUI Top-Level Signals Soft IP Implementation
SOPC Builder User
xaui_rx_serial_data[3:0]
xaui_tx_serial_data[3:0]
reconfig_fromgxb[67:0]
cal_blk_powerdown
reconfig_togxb[3:0]
rx_channelaligned
rx_syncstatus[7:0]
rx_errdetect[7:0]
gxb_powerdown
pll_powerdown
rx_disperr[7:0]
Guide.
pll_locked
rx_ready
tx_ready
Altera Transceiver PHY IP Core User Guide
Transceiver
Serial Data
Optional
Rx Status
Optional
Controller
Channel
PMA
Figure 4–4
4–5