IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 59

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: Interlaken PHY IP Core
Interface
Table 5–7. Interlaken Registers (Part 2 of 3)
December 2010 Altera Corporation
0x044
0x061
0x064
0x065
0x066
00x067
Word
Addr
[31:4,0]
[31:0]
[31:0]
[31:0]
[31:0]
[31:0]
Bits
[1]
[2]
[3]
R/W
RW
RW
RW
RW
RW
RW
RW
R
R
reset_fine_control
reset_tx_digital
reset_rx_analog
reset_rx_digital
phy_serial_loopback
pma_rx_set_locktodata
pma_rx_set_locktoref
pma_rx_is_lockedtodata
pma_rx_is_lockedtoref
Register Name
PMA Control and Status Registers
You can use the reset_fine_control register to create
your own reset sequence. The reset control module,
illustrated in
reset sequence at power on and whenever the
phy_mgmt_clk_reset is asserted. Bits [31:4, 0] are
reserved.
Writing a 1 causes the internal TX digital reset signal to be
asserted, resetting all channels enabled in
reset_ch_bitmask. You must write a 0 to clear the
reset condition.
Writing a 1 causes the internal RX digital reset signal to be
asserted, resetting the RX analog logic of all channels
enabled in reset_ch_bitmask. You must write a 0 to
clear the reset condition.
Writing a 1 causes the RX digital reset signal to be asserted,
resetting the RX digital channels enabled in
reset_ch_bitmask. You must write a 0 to clear the
reset condition.
Writing a 1 to channel <n> puts channel <n> in serial
loopback mode.
When set, programs the RX CDR PLL to lock to the
incoming data. Bit <n> corresponds to channel <n>.
When set, programs the RX CDR PLL to lock to the
reference clock. Bit <n> corresponds to channel <n>.
When asserted, indicates that the RX CDR PLL is locked to
the RX data, and that the RX CDR has changed from LTR to
LTD mode. Bit <n> corresponds to channel <n>.
When asserted, indicates that the RX CDR PLL is locked to
the reference clock. Bit <n> corresponds to channel <n>.
Figure 1–1 on page
Description
Altera Transceiver PHY IP Core User Guide
1–2, performs a standard
5–7