IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 105

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 9: Transceiver Reconfiguration Controller
Steps to Achieve PMA Controls Reconfiguration
Table 9–1. Dynamic Reconfiguration Control and Status Registers (Part 2 of 2)
Steps to Achieve PMA Controls Reconfiguration
December 2010 Altera Corporation
0x10C
0x110
Offset
[15:0]
[31:16]
Bits
R/W
RW
You can use the Avalon-MM interface to change settings for the TX and RX channels.
Complete the following steps to reconfigure a setting:
1. Write the channel to be configured to the logical_channel_address.
2. Set the tx_rx_word_offset, indicating which PMA analog control is to be
3. Write the reconfiguration data to the reconfig_data register.
4. Set the read or write bit to 1.
5. Read the busy bit until it is deasserted, indicating that the operation has
—
changed.
completed.
reconfig_data
Reserved
eye_monitor
Register Name
Reconfiguration data.
For complete information about the EyeQ interface and
registers refer to, “EyeQ Interface Register Mapping” in
the
volume 2 of the Stratix IV Device Handbook.
Stratix IV Dynamic Reconfiguration
Altera Transceiver PHY IP Core User Guide
Description
—
chapter in
9–3