IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 56

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–4
Table 5–4. Avalon-ST TX Signals
Altera Transceiver PHY IP Core User Guide
tx_parallel_data[63:0]
tx_parallel_data[64]
tx_parallel_data[65]
tx_ready
tx_datain_bp
Signal Name
Avalon-ST TX Interface
f
For more information about _hw.tcl, files refer to the
chapter in Volume 4 of the Quartus II Handbook.
Figure 5–2. Top-Level Interlaken Signals
Note to
(1) <n> = the number of channels in the interface, so that the width of tx_data in 4-channel instantiation is [263:0].
The following sections describe the signals in each interface.
Table 5–4
Avalon-MM PHY
Management
Interface
TX to/ from
RX from/to
Avalon-ST
Avalon-ST
MAC
MAC
PLL
Figure
Direction
lists the signals in the Avalon-ST TX interface.
Source
Source
Sink
Sink
Sink
5–2:
Avalon-ST data driven from the FPGA fabric.
Indicates whether tx_parallel_data[63:0] represents command or
data. When 0, tx_parallel_data[63:0]is data. When 1,
tx_parallel_data[63:0] is control.
When asserted, indicates that tx_parallel_data[63:0] is valid.
When asserted, indicates that the TX interface has exited the reset state.
When asserted, indicates that this Avalon-ST sink interface is ready to
receive data. The readyLatency on this Avalon-ST interface is 0 cycles;
consequenty, the application drives tx_parallel_data[63:0]as soon as
tx_ready is asserted. (tx_datain_bp is connected to the ~partialfull
of the TX FIFO, so that when tx_datain_bp is deasserted the TX FIFO is
almost full and back pressures the MAC.)
tx_parallel_data<n>[65:0]
tx_ready
tx_datain_bp<n>
tx_clkout<n>
tx_user_clkout
rx_parallel_data<n>[71:0]
rx_ready
rx_clkout<n>
rx_fifo_clr<n>
rx_dataout_bp<n>
phy_phy_mgmt_clk
phy_mgmt_clk_reset
phy_mgmt_address[8:0]
phy_mgmt_writedata[31:0]
phy_mgmt_readdata[31:0]
phy_mgmt_write
phy_mgmt_read
phy_mgmt_waitrequest
pll_ref_clk
Interlaken Top-Level Signals
(Note 1)
Description
rx_serial_data<n>
tx_serial_data<n>
Component Interface Tcl Reference
rx_coreclkin
tx_coreclkin
December 2010 Altera Corporation
Chapter 5: Interlaken PHY IP Core
High Speed
For Deskew
Serial I/O
(Optional)
Interface